📄 mplregs.h
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#define PINT_ACEN 0x00020000 // phy int auto clear (R/W)
// PHY Configuration - FM
#define AUTO_DUP 0x01000000 // Ena Auto Full duplex (R/W)
#define ANEG_DN 0x08000000 // Auto Neg done
#define POL_10M 0x10000000 // 10M with reverse polarity detected (RO)
#define FULLDUP_STS 0x20000000 // full duplex indication from phy (RO)
#define LINKSPEED100 0x40000000 // 100 Mbps indication from phy (RO)
#define LINKGOOD_STS 0x80000000 // good link indication from phy (RO)
//***************************************************************
// MEAR - MII / EEPROM Access Register
//***************************************************************
#define EEPROM_DI 0x00000001 // EEPROM data in (ouR data out) (R/W)
#define EEPROM_DO 0x00000002 // EEPROM data out (our data in) (RO)
#define EEPROM_CLK 0x00000004 // EEPROM clock (R/W)
#define EEPROM_CS 0x00000008 // EEPROM chip select (R/W)
#define MDIO 0x00000010 // MII management data input/output (R/W)
#define MDDIR 0x00000020 // MII management data dir, 1 = out (R/W)
#define MDCLK 0x00000040 // MII management data clock (R/W)
#define EEPROM_WRITE 0x00000140 // EEPROM Write Command
#define EEPROM_READ 0x00000180 // EEPROM Read Command
#define EEPROM_ERASE 0x000001C0 // EEPROM Erase Command
enum EEPROM_Cmds {
EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
};
#define MII_READ 0x6003FFFF
#define MII_WRITE 0x50020000
#define MII_ADDR_OFF 23
#define MII_REG_OFF 18
#define MII_CMD_OFF 16
//***************************************************************
// MTSCR - MAC Test Control Register
//***************************************************************
#define EEBIST_FAIL 0x00000001 // EE Bist fail indication (RO)
#define EEBIST_EN 0x00000002 // Enable EEPROM BIST (R/W)
#define EELOAD_EN 0x00000004 // Enable EEPROM Load (R/W)
#define RBIST_RXRFAIL 0x00000008 // RX FIlter RAM BIST Fail (RO)
#define RBIST_TXFAIL 0x00000010 // TX FIFO Fail (RO)
#define RBIST_RXFAIL 0x00000020 // RX FIFO BIST Fail (RO)
#define RBIST_DONE 0x00000040 // SRAM BIST Done (RO)
#define RBIST_EN 0x00000080 // SRAM BIST Enable (R/W)
#define RBIST_MODE 0x00000100 // SRAM BIST Mode - Reserved NSC (R/W)
#define RBIST_CLKD 0x00000200 // SRAM BIST Clock - Reserved NSC (R/W)
#define RBIST_RST 0x00000400 // SRAM BIST Reset (R/W)
#define RBIST_REL 0x00000800 // SRAM BIST Reliablity Mode (R/W)
#define FORCE_CRS 0x00001000 // Force CRS (R/W)
#define RXFIFO2K 0x00002000 // Select 2KB RX FIFO (R/W)
//***************************************************************
// ISR/IMR - Interrupt bit definitions
//***************************************************************
#define RXOK 0x00000001 // RX OK interrupt
#define RXDESC 0x00000002 // RX descriptor interrupt
#define RXERR 0x00000004 // RX packet error
#define RXEARLY 0x00000008 // RX Early Threshold
#define RXIDLE 0x00000010 // RX Idle
#define RXOVERUN 0x00000020 // RX Overrun
#define TXOK 0x00000040 // TX OK interrupt
#define TXDESC 0x00000080 // TX descriptor interrupt
#define TXERR 0x00000100 // TX packet error
#define TXIDLE 0x00000200 // TX idle
#define TXUNDERRUN 0x00000400 // TX underrun
#define MIBSTATS 0x00000800 // MIB statistics service
#define SW_INT 0x00001000 // software interrupt
#define WOL_EVENT 0x00002000 // Wake-On-LAN power management event
#define PHYSTSCHANGE 0x00004000 // phy status change
#define HIORDER_INT 0x00008000 // one of the following int's occured
#define RXSTSFIFO_OVRN 0x00010000 // rx status fifo overrun
#define PCI_TARGABORT 0x00100000 // received PCI target abort
#define PCI_MSTRABORT 0x00200000 // generated PCI master abort
#define PCI_SERR 0x00400000 // generated PCI system error
#define PCI_PARERR 0x00800000 // detected PCI parity error
#define RXRST_COMPLETE 0x01000000 // receive reset complete
#define TXRST_COMPLETE 0x02000000 // transmit reset complete
#define TXDESC0 0x04000000 // Tx Descriptor for priority Q 0
#define TXDESC1 0x08000000 // Tx Descriptor for priority Q 1
#define TXDESC2 0x10000000 // Tx Descriptor for priority Q 2
#define TXDESC3 0x20000000 // Tx Descriptor for priority Q 3
#define TXDESC_MASK 0x3C000000 // Tx Descriptor INTR mask
#define TXDESC_OFF 26 // Tx Descriptor INTR offset
//**************************************************************
// IER - Interrupt Enable Register
//***************************************************************
#define INT_EN 0x00000001 // Intr Ena (0 masks all ints) (R/W)
#define AUTODISABLEINT_EN 0x00000002 // en auto disable (read of ISR disables
// all int's until INT_EN set (R/W)
// bits 2-31 (reserved)
//**************************************************************
// IHR - Interrupt Holdoff Register
//***************************************************************
#define INTHLD_VAL_MASK 0x000000FF // mask for interrupt holdoff value (R/W)
#define STARTHLDOFFON1INT 0x00000100 // start interrupt holdoff on 1st int
// (if clr, hold begins on int en) (R/W)
#define INTHLDTMR_4US 0x00000200 // set holdoff tick to 4us (if clear,
// tick=100us (R/W)
// bits 10-15 (reserved)
#define INTHLDCNCL_RXPKTS_SHIFT 16
#define INTHLDCNCL_RXPKTS_MASK 0x001F0000 // # of rcv packets that will
// prematurely terminate intr
// holdoff (R/W)
#define INTHLDCNCL_TXPKTS_SHIFT 21
#define INTHLDCNDL_TXPKTS_MASK 0x03E00000 // # of rcv packets that will
// prematurely terminate intr
// holdoff (R/W)
// bits 26-31 (reserved)
#define MAX_HOLD_TIME (0xFF*100) // Max intr hold timeout value
// 255*100usec
#define HOLD_TIME_MASK 0xFFFFFF00 // Hold time mask
//***************************************************************
// TXCFG - Transmit Configuration Register
//***************************************************************
#define MXDMA4 0x00100000 // 4 bytes (R/W)
#define MXDMA8 0x00200000 // 8 bytes (R/W)
#define MXDMA16 0x00300000 // 16 bytes (R/W)
#define MXDMA32 0x00400000 // 32 bytes (R/W)
#define MXDMA64 0x00500000 // 64 bytes (R/W)
#define MXDMA128 0x00600000 // 128 bytes (R/W)
#define MXDMA256 0x00700000 // 256 bytes (R/W)
#define MXDMA512 0x00000000 // 512 bytes (R/W)
#define TXDMA4 0x00020000 // scale MXDMA table value setting by 4
#define BOFF_CONT 0x00040000 // enable backoff continuos
#define BLINDTX_EN 0x00080000 // enable blind transmit (R/W) !825
#define EXC_COLN_RETRY 0x00800000 // en excessive collision retry (R/W)
#define AUTOTXPAD_EN 0x10000000 // en Automatic Tx Padding (R/W)
#define LOOPBACK_EN 0x20000000 // enable MAC loopback mode (R/W)
#define SQE_IGNORE 0x40000000 // dis SQE (heart beat) test (R/W)
#define CARRIER_IGNORE 0x80000000 // carrier sense ignore (R/W)
#define TXDRAIN_MASK 0x0000003F // transmit drain thresh mask
#define TXFILL_MASK 0x00003F00 // transmit fill thresh mask
#define TXFILL_SHIFT 8
#define TXMXDMA_MASK 0x00700000 // max tx DMA mask
#define TXSET_MASK (TXDMA4 | TXDRAIN_MASK | TXFILL_MASK | TXMXDMA_MASK)
//***************************************************************
// GPIOR - General Purpose I/O Register
//***************************************************************
#define GP1_OUT 0x00000001 // General purpose Pin 1 Output (R/W)
#define GP2_OUT 0x00000002 // General purpose Pin 2 Output (R/W)
#define GP3_OUT 0x00000004 // General purpose Pin 3 Output (R/W)
#define GP4_OUT 0x00000008 // General purpose Pin 4 Output (R/W)
#define GP1_OE 0x00000010 // General purpose Pin 1 Output Enable (R/W)
#define GP2_OE 0x00000020 // General purpose Pin 2 Output Enable (R/W)
#define GP3_OE 0x00000040 // General purpose Pin 3 Output Enable (R/W)
#define GP4_OE 0x00000080 // General purpose Pin 4 Output Enable (R/W)
#define GP1_IN 0x00000100 // General purpose Pin 1 Input (RO)
#define GP2_IN 0x00000200 // General purpose Pin 2 Input (RO)
#define GP3_IN 0x00000400 // General purpose Pin 3 Input (RO)
#define GP4_IN 0x00000800 // General purpose Pin 4 Input (RO)
//**************************************************************
// RXCFG - Receive Configuration Register
//***************************************************************
#define RXDRAIN_SHIFT 1
#define RXDRAIN_MASK 0x0000003E // rx drain threshold mask
#define RXDMA4 0x00040000 // scale MXDMA table value setting by 4
#define DMA_USECACHESIZ_EN 0x00080000 // rx dma multiples of cacheline size
// (R/W)
#define RXMXDMA_MASK 0x00700000 // max rx DMA mask
#define RXSET_MASK (RXDRAIN_MASK | RXMXDMA_MASK | RXDMA4)
// max rx DMA burst sizes...use TXCFG MXDMAxxx definitions
#define ACCEPT_INRNG_LENERR 0x04000000 // accept in-range-length error'd
// pkts (R/W)
#define ACCEPT_LONGPKT 0x08000000 // accept long packets (R/W)
#define FULLDUPLEX_EN 0x10000000 // en. full duplex (R/W)
#define STRIPCRC_EN 0x20000000 // en strip CRC (R/W)
#define ACCEPT_RUNTS 0x40000000 // accept runts (R/W)
#define ACCEPT_CRCALIGNERR 0x80000000 // accept CRC and alignment err's (R/W)
//**************************************************************
// CCSR - PME Backdoor Register
//***************************************************************
#define PMEEN 0x00000100 // PME Enable (R/W) -
// - Mirrored from PMCSR
#define PMESTS 0x00008000 // PME (sticky) Status (R/W)
// - Mirrored from PMCSR
//**************************************************************
// WCSR - Wake Command / Status Register.
//***************************************************************
#define WAKEON_PHYSTSCHNG 0x00000001 // wake on phy sts change int (R/W)
#define WAKEON_UNICAST 0x00000002 // wake on any unicast pkt (R/W)
#define WAKEON_MULTICAST 0x00000004 // wake on multicast pkt (R/W)
#define WAKEON_BROADCAST 0x00000008 // wake on broadcast pkt (R/W)
#define WAKEON_ARPPKT 0x00000010 // wake on TCP/IP ARP (R/W)
#define WAKEON_PATRN0 0x00000020 // wake on pattern #0 match (R/W)
#define WAKEON_PATRN1 0x00000040 // wake on pattern #1 match (R/W)
#define WAKEON_PATRN2 0x00000080 // wake on pattern #2 match (R/W)
#define WAKEON_PATRN3 0x00000100 // wake on pattern #3 match (R/W)
#define WAKEON_MAGICPKT 0x00000200 // wake on magic pkt (R/W)
#define MAGICPKT_SECURE_EN 0x00000400 // en magic pkt secure on (R/W)
#define WAKEON_PATRN4 0x00000800 // wake on pattern #4 match (R/W)
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