mplregs.h

NATIONAL公司DP83816芯片Linux下驱动

//**********************************************************************
//
//  MPLREGS.H
//
//  Copyright (c) 2004 National Semiconductor Corporation.
//  All Rights Reserved
//
//  Defines the device registers (MAC and PHY)
//
//**********************************************************************

#ifndef _MPLREGS_H
#define _MPLREGS_H

// Reset intervals
#define RESETINTERVAL_MAC   1000 // interval from MAC reset (in usec)
#define EELOADINTERVAL      1000 // interval from EELOAC (usec)
#define RESETINTERVAL_PHY   1000 // interval from MAC reset (in usec)

// MacPhy PHY IDs
#define MP_PHY_ID1        0x2000
#define MP_PHY_REV        0x5C20 //Prior to MP3
#define ASPEN_PHY_REV     0x5C90
#define PHY_MII_REG_BASE  0x80 

// MacPhy MAC IDs
#define MPI_C_MAC_ID      0x0302 // Macphyter-I Rev-C
#define MPI_D_MAC_ID      0x0403 // Macphyter-I Rev-D
#define MPII_A4_MAC_ID    0x0504 // Macphyter-II Rev-A4
#define MPII_A5_MAC_ID    0x0505 // Macphyter-II Rev A5
#define MPIII_MAC_ID      0x0601 // Macphyter-III

// All packed on byte boundaries
#pragma pack(1)

//    Operational Register Map for MacPhyter2/3
typedef volatile struct _DP8381xOpRegs {

    // Basic MAC (0x00 to 0x5C)
    NS_UINT32   CR;         // Command register 
    NS_UINT32   CFG;        // Cfg and media status 
    NS_UINT32   MEAR;       // Mii, EEprom Access 
    NS_UINT32   MTSCR;      // MAC Test Control 
    NS_UINT32   ISR;        // Interrupt Status 
    NS_UINT32   IMR;        // Interrupt Mask 
    NS_UINT32   IER;        // Interrupt enable 
    NS_UINT32   IHR;        // Interrupt holdoff 
    NS_UINT32   TXDP;       // Tx descriptor ptr, queue 0 
    NS_UINT32   TXCFG;      // Transmit configuration 
    NS_UINT32   pad1;       // Reserved 
    NS_UINT32   GPIOR;      // General I/O pin control 
    NS_UINT32   RXDP;       // Rx descriptor ptr, queue0 
    NS_UINT32   RXCFG;      // Receive configuration 
    NS_UINT32   pad2;       // Reserved 
    NS_UINT32   CCSR;       // PME backdoor 
    NS_UINT32   WCSR;       // Wake-on-LAN command Status 
    NS_UINT32   PCR;        // Pause frame control status 
    NS_UINT32   RFCR;       // Receive filter control 
    NS_UINT32   RFDR;       // Receive filter data 
    NS_UINT32   BRAR;       // Boot rom address 
    NS_UINT32   BRDR;       // Boot rom data 
    NS_UINT32   SRR;        // Silicon revision 
    NS_UINT32   MIBC;       // MIB statistics Control 
    
    // MIB regs (0x60 to 0x7C)
    NS_UINT32   RXE;        // Packets recd with errors 
    NS_UINT32   RXFCS;      // Packets recd with frame check seq err 
    NS_UINT32   RXM;        // Packets missed due to FIFO overruns 
    NS_UINT32   RXFAE;      // Packets recd with frame alignment err 
    NS_UINT32   RXS;        // Packets recd with symbol err 
    NS_UINT32   RXF;        // Packets recd with len > 1518 
    NS_UINT32   TXSQE;      // Packets with loss of collision during 
                            //  transmission 
    NS_UINT32   RXIRL;      // Packets recd with InRange length errs 

    // Internal PHY (0x80 to 0x9C)
    NS_UINT32   BMCR;       // Basic Mode Control Register 
    NS_UINT32   BMSR;       // Basic Mode Status Register 
    NS_UINT32   PHYIDR1;    // PHY Id reg1 
    NS_UINT32   PHYIDR2;    // PHY Id reg2 
    NS_UINT32   ANAR;       // Auto-Neg Adv reg 
    NS_UINT32   ANLPAR;     // Auto-Neg Link partner reg 
    NS_UINT32   ANER;       // Auto-Neg expansion reg 
    NS_UINT32   ANNPTR;     // Auto-Neg next page TX 

    // Priority Queuing (0xA0 to 0xAC)
    NS_UINT32   TXDP1;      // Tx descriptor ptr, queue1 
    NS_UINT32   TXDP2;      // Tx descriptor ptr, queue2 
    NS_UINT32   TXDP3;      // Tx descriptor ptr, queue3 
    NS_UINT32   PQCR;       // Prority Queue Control reg

    // VLAN control (0xB0 to 0xB4)
    NS_UINT32   VRCR;       // VLAN receive control 
    NS_UINT32   VTCR;       // VLAN transmit control 

    NS_UINT32   pad3;       // Reserved 
    NS_UINT32   pad4;       // Reserved 

    // PHY Status (0xC0)
    NS_UINT32   PHYSTS;     // Phy Status Register

    // PHY MII Regs (0xC4 and 0xC8)
    NS_UINT32   MICR;       // Phy MII Interrupt Control
    NS_UINT32   MISR;       // Phy MII Interrupt Status

    // PHY Interal Regs
    NS_UINT32   PAGE;       // 0xCC page select
    union _RegD0 {
        NS_UINT32  FCSCR;   // 0xD0 (Page 0) false carrier sense counter 
        NS_UINT32  FCOCTL;  // 0xD0 (Page 1) FCO control 
    } RegD0;
#define FCSCR  RegD0.FCSCR
#define FCOCTL RegD0.FCOCTL

    union _RegD4 {
        NS_UINT32  RECR;    // 0xD4 (Page 0) receiver error counter 
        NS_UINT32  TMR;     // 0xD4 (Page 1) test mode 
    } RegD4;
#define RECR RegD4.RECR 
#define TMR RegD4.TMR

    union _RegD8 {
        NS_UINT32  PCS;     // 0xD8 (Page 0) PCS sub layer config & status 
        NS_UINT32  BGR;     // 0xD8 (Page 1) band gap reference 
    } RegD8;
#define PCS RegD8.PCS
#define BGR RegD8.BGR

    union _RegDC {
        NS_UINT32  RBR;     // 0xDC (Page 0) RMII & bypass 
        NS_UINT32  CRM;     // 0xDC (Page 1) CRM 
    } RegDC;
#define RBR RegDC.RBR
#define CRM RegDC.CRM

    NS_UINT32  CDCT12;      // 0xE0 (Page 1) CD test control 2 

    union _RegE4 {
        NS_UINT32  PHYCTL;  // 0xE4 (Page 0) phy control 
        NS_UINT32  PMDCSR;  // 0xE4 (Page 1) PMD control/status 
    } RegE4;
#define PHYCTL RegE4.PHYCTL
#define PMDCSR RegE4.PMDCSR

    union _RegE8 {
        NS_UINT32  TENBT;   // 0xE8 (Page 0) 10BaseT status/control 
        NS_UINT32  PGMCGM;  // 0xE8 (Page 1) PGM/CGM control 
    } RegE8;
#define TENBT RegE8.TENBT
#define PGMCGM RegE8.PGMCGM

    union _RegEC {
        NS_UINT32  CDCTL1;  // 0xEC (Page 0) CD test control 1 
        NS_UINT32  DSPTST;  // 0xEC (Page 1) DSP test 
    } RegEC;
#define CDCTL1 RegEC.CDCTL1
#define DSPTST RegEC.DSPTST

    NS_UINT32  EXTCFG;      // 0xF0 (Page 1) extended config 
    NS_UINT32  DSPCFG;      // 0xF4 (Page 1) DSP config 
    NS_UINT32  SDCFG;       // 0xF8 (Page 1) signal detect config. 
    NS_UINT32  TDATA;       // 0xFC (Page 1) test data 

} DP8381xOpRegs;

#pragma pack()  // reset back to the default packing 



// OPERATIONAL REGISTER  BIT DEFINITIONS
// (R/W = read/write, RO = read only, ROSC = read only, self-clearing,
//  WR0 = write, read back 0, !825 = DP83825 only)

//***************************************************************
// CR - command register bit definitions
//***************************************************************
#define TX_EN           0x00000001      // transmitter enable (R/W) 
#define TX_DIS          0x00000002      // transmitter disable (WR0) 
#define RX_EN           0x00000004      // receiver enable (R/W) 
#define RX_DIS          0x00000008      // receiver disable (WR0) 
#define TXRESET         0x00000010      // transmitter reset (WR0) 
#define RXRESET         0x00000020      // receiver reset (WR0) 
                                        // bit 6 (reserved) 
#define SWINT           0x00000080      // software interrupt 
#define SOFTRESET       0x00000100      // soft reset (W read 0  when comp) 
#define TXQUEUE_MASK    0x00001E00      // Tx priority queue mask 
#define TXQUEUE0_EN     0x00000200      // Tx Priority Queue 0 (R/W) 
#define TXQUEUE1_EN     0x00000400      // Tx Priority Queue 1 (R/W) 
#define TXQUEUE2_EN     0x00000800      // Tx Priority Queue 2 (R/W) 
#define TXQUEUE3_EN     0x00001000      // Tx Priority Queue 3 (R/W) 
#define TX_PQUEUE_OFF   9               // Bit Offset for Tx Pri Q setting 


//***************************************************************
// CFG - Configuration and Media Status Register 
//***************************************************************
#define BIG_ENDIAN      0x00000001    // big endian (DMA only) (R/W)
#define TMRTEST         0x00000002    // speeds up 100us internal timer to 4us
#define BROM_DIS        0x00000004    // disable Boot ROM I/F (R/W) 
#define SERR_ON_PAR_ERR 0x00000008    // SERR on PCI parity err (R/W) 
#define ABORT_ON_EXCESSIVE_DEF 0x00000010 // abrt on excessive deferral (R/W) 
#define OOWTMR_AT_PRESTRT 0x00000020  // out-of-window at preamble start (R/W) 
#define SINGLETXBCKOFF  0x00000040    // Single IFG tx Backoff (R/W) 
#define PCIREQ_WEAK     0x00000080    // conservative PCI bus req algo (R/W) 
#define EXTENDEDDESC_EN 0x00000100    // Extended descriptor format en (R/W) 
#define PHY_DIS         0x00000200    // dise phy (deassert mii RXEN) (R/W) 
#define PHY_RST         0x00000400    // reset phy (assert PHYRST_N) (R/W) 
#define BEM_REG         0x00000800    // Big endian reg mode (R/W)-DP83818
#define EXT_PHY         0x00001000    // Enable External Phy Support (R/W) 

// Auto-Neg Select - FM

#define PAUSE_ADV       0x00010000    // pause Advertise (R/W)