clock_generator.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module clk_generator(CLK_IN,CLK_RST,SYS_CLK,MAC_CLK,DIN_CLK,CB_CLK,SYS_CLK_D,
                        LOCKED);
    input CLK_IN;
    input CLK_RST;

    output SYS_CLK;
    output MAC_CLK;
    output DIN_CLK;
    output CB_CLK;
    output SYS_CLK_D;
    output LOCKED;

    wire RST;                                 //RST is the core reset signal enabled with high level
    wire LOCKED_OUT1;                         //Output of the DCM1 that activates after the DCM has achieved lock
    wire SYS_CLK;						             //Clock divide output of the DCM1 by 2
    wire CB_CLK;                              //Clock double output of the DCM1
    wire DCM2_CLK;                            //Frequency synthesizer output to the DCM1 by 2/3 
    wire SYS_CLK_D;                           //The clock output same as input clock	of DCM1
    wire CLK_IN2;                             //Clock for generating MAC_CLK
    reg LOCKED;                               
    reg MAC_CLK;                              //Clock divide output of the DCM1 by 8
    wire DIN_CLK;                             
    reg lock_reg;
    reg lock_reg1;
    reg lock_reg2;
    assign DCM2_CEN=~lock_reg2;               
    assign RST=~CLK_RST;                      //RST is the core reset signal enabled with high level.
    wire RST2;
	 assign RST2=lock_reg2;
	 
//Digital clock management block1 is used to generate clocks with the frequency
//of 20MHz, 40MHz, 80 MHz and 60MHz. The last one will be used as the clock to 
//generator 7.5MHz.

wire clk_reg;
DCM1 U_DCM1 (
    .RST_IN(RST), 
    .LOCKED_OUT(LOCKED_OUT1), 
    .CLKIN_IN(CLK_IN), 
    .CLKDV_OUT(SYS_CLK), 
    .CLK2X_OUT(CB_CLK), 
    .CLKFX_OUT(DCM2_CLK), 
    .CLK0_OUT(SYS_CLK_D), 
    .CLKIN_IBUFG_OUT(clk_reg)
    );


BUFG DCM2_CLK_BUFG(
    .I (DCM2_CLK),
    .O (CLK_IN2)
      );
BUFG CLK_BUFG(
    .I (DCM2_CLK),
    .O (DIN_CLK)
      );


always @(posedge clk_reg or negedge CLK_RST)  //delay lock_reg for 3 clock cycle
	begin
		if(!CLK_RST)
			begin
				lock_reg<=0;
				lock_reg1<=0;
				lock_reg2<=0;
			end
		else
			begin
				lock_reg<=LOCKED_OUT1;
				lock_reg1<=lock_reg;
				lock_reg2<=lock_reg1;
			end
	end  
	

reg [3:0]count;

always @ (negedge RST2 or posedge CLK_IN2)  // generater counter to devide the CLK_IN2 and generate LOCKED at appropriate time
begin
  if(!RST2)
   begin
	 count<=4'b0;
	 LOCKED<=1'b0;
	end
  else
    if (count==4'b0111)
	   count<=4'b0;
	 else if(count==4'b0001)
	   begin
		LOCKED<=1'b1;
	   count<=count+1;
		end
	 else
      count<=count+1;	 
   begin
	end
end

always @ (negedge RST2 or posedge CLK_IN2)    //deviding CLK_IN2 by 8 to generate MAC_CLK
begin
  if(!RST2)
    MAC_CLK<=1'b0;
  else
	 if (count<=4'b0011)
	    MAC_CLK<=1'b0;
	 else
       MAC_CLK<=1'b1;		 
   begin
	end
end

endmodule