counter_30.xco

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

# Xilinx CORE Generator 6.1.03i; Cores Update # 1.01
# Username = Administrator
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\Xilinx\bin\OFDM_Trans
# ExpandedProjectPath = C:\Xilinx\bin\OFDM_Trans
# OverwriteFiles = true
# Core name: counter_30
# Number of Primitives in design: 31
# Number of CLBs used in design: 3
# Number of Slices used in design: 9
# Number of LUT sites used in design: 16
# Number of LUTs used in design: 16
# Number of REG used in design: 6
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "default" = (0, 0) to (1, 3) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Binary_Counter Spartan3 Xilinx,_Inc. 6.0
CSET ce_override_for_load = false
CSET async_init_value = 0
CSET create_rpm = true
CSET clock_enable = true
CSET load = false
CSET ce_overrides = sync_controls_override_ce
CSET load_sense = active_high
CSET sync_init_value = 0
CSET operation = up
CSET threshold_1 = true
CSET threshold_0 = false
CSET count_style = count_by_constant
CSET restrict_count = true
CSET count_by_value = 1
CSET component_name = counter_30
CSET threshold_early = true
CSET asynchronous_settings = clear
CSET threshold_1_value = 2
CSET count_to_value = 1D
CSET threshold_0_value = MAX
CSET threshold_options = non_registered
CSET set_clear_priority = clear_overrides_set
CSET output_width = 5
CSET synchronous_settings = none
GENERATE