dint_ram2.xco

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

# Xilinx CORE Generator 6.1.03i; Cores Update # 1.01
# Username = Owner
# COREGenPath = D:\Study-program\Xilinx\coregen
# ProjectPath = D:\Study-program\Xilinx\myworks\OFDM_Trans
# ExpandedProjectPath = D:\Study-program\Xilinx\myworks\OFDM_Trans
# OverwriteFiles = true
# Core name: dint_ram2
# Number of Primitives in design: 8
# Number of CLBs used in design: 4
# Number of Slices used in design: 5
# Number of LUT sites used in design: 8
# Number of LUTs used in design: 4
# Number of REG used in design: 2
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 2
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "default" = (0, 0) to (4, 1) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Distributed_Memory Spartan3 Xilinx,_Inc. 6.0
CSET single_port_output_clock_enable = false
CSET create_rpm = true
CSET output_options = registered
CSET reset_qspo = false
CSET dual_port_output_clock_enable = false
CSET dual_port_address = non_registered
CSET sync_reset_qdpo = false
CSET default_data = 0
CSET ce_overrides = sync_controls_overrides_ce
CSET memory_type = dual_port_ram
CSET common_output_ce = false
CSET data_width = 1
CSET component_name = dint_ram2
CSET qualify_we_with_i_ce = false
CSET sync_reset_qspo = false
CSET read_enable = false
CSET common_output_clk = false
CSET multiplexer_construction = lut_based
CSET input_options = non_registered
CSET reset_qdpo = true
CSET input_clock_enable = false
CSET depth = 32
GENERATE