rcount_1.vhd

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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-- You must compile the wrapper file rcount_1.vhd when simulating
-- the core, rcount_1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY rcount_1 IS
	port (
	Q: OUT std_logic_VECTOR(9 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic;
	ACLR: IN std_logic);
END rcount_1;

ARCHITECTURE rcount_1_a OF rcount_1 IS

component wrapped_rcount_1
	port (
	Q: OUT std_logic_VECTOR(9 downto 0);
	CLK: IN std_logic;
	CE: IN std_logic;
	ACLR: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_rcount_1 use entity XilinxCoreLib.C_COUNTER_BINARY_V6_0(behavioral)
		generic map(
			c_count_mode => 0,
			c_has_aset => 0,
			c_load_enable => 1,
			c_load_low => 0,
			c_count_to => "0101111111",
			c_sync_priority => 1,
			c_has_iv => 0,
			c_has_sclr => 0,
			c_restrict_count => 1,
			c_width => 10,
			c_has_q_thresh1 => 0,
			c_has_q_thresh0 => 0,
			c_thresh1_value => "1111111111111111",
			c_enable_rlocs => 1,
			c_has_load => 0,
			c_has_up => 0,
			c_thresh_early => 1,
			c_has_thresh1 => 0,
			c_has_thresh0 => 0,
			c_ainit_val => "0000",
			c_has_ce => 1,
			c_pipe_stages => 0,
			c_has_aclr => 1,
			c_sync_enable => 0,
			c_has_ainit => 0,
			c_sinit_val => "0",
			c_has_sset => 0,
			c_has_sinit => 0,
			c_count_by => "0001",
			c_has_l => 0,
			c_thresh0_value => "1111111111111111");
BEGIN

U0 : wrapped_rcount_1
		port map (
			Q => Q,
			CLK => CLK,
			CE => CE,
			ACLR => ACLR);
END rcount_1_a;

-- synopsys translate_on