dint_ram2.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file dint_ram2.v when simulating
// the core, dint_ram2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Guide".

module dint_ram2 (
	A,
	CLK,
	D,
	WE,
	DPRA,
	QDPO_CLK,
	QDPO,
	QSPO,
	QDPO_RST);    // synthesis black_box

input [4 : 0] A;
input CLK;
input [0 : 0] D;
input WE;
input [4 : 0] DPRA;
input QDPO_CLK;
output [0 : 0] QDPO;
output [0 : 0] QSPO;
input QDPO_RST;

// synopsys translate_off

	C_DIST_MEM_V6_0 #(
		5,	// c_addr_width
		"0",	// c_default_data
		1,	// c_default_data_radix
		32,	// c_depth
		1,	// c_enable_rlocs
		1,	// c_generate_mif
		1,	// c_has_clk
		1,	// c_has_d
		0,	// c_has_dpo
		1,	// c_has_dpra
		0,	// c_has_i_ce
		1,	// c_has_qdpo
		0,	// c_has_qdpo_ce
		1,	// c_has_qdpo_clk
		1,	// c_has_qdpo_rst
		0,	// c_has_qdpo_srst
		1,	// c_has_qspo
		0,	// c_has_qspo_ce
		0,	// c_has_qspo_rst
		0,	// c_has_qspo_srst
		0,	// c_has_rd_en
		0,	// c_has_spo
		0,	// c_has_spra
		1,	// c_has_we
		1,	// c_latency
		"dint_ram2.mif",	// c_mem_init_file
		2,	// c_mem_type
		0,	// c_mux_type
		0,	// c_qce_joined
		0,	// c_qualify_we
		0,	// c_read_mif
		0,	// c_reg_a_d_inputs
		0,	// c_reg_dpra_input
		0,	// c_sync_enable
		1)	// c_width
	inst (
		.A(A),
		.CLK(CLK),
		.D(D),
		.WE(WE),
		.DPRA(DPRA),
		.QDPO_CLK(QDPO_CLK),
		.QDPO(QDPO),
		.QSPO(QSPO),
		.QDPO_RST(QDPO_RST),
		.SPRA(),
		.I_CE(),
		.QSPO_CE(),
		.QDPO_CE(),
		.RD_EN(),
		.QSPO_RST(),
		.QSPO_SRST(),
		.QDPO_SRST(),
		.SPO(),
		.DPO());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of dint_ram2 is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of dint_ram2 is "black_box"

endmodule