dint_ram.edn

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

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      (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000"))
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      (property WRITE_MODE_A (string "WRITE_FIRST"))
      (property INIT_A (string "0"))
      (property SRVAL_A (string "0"))
      (property WRITE_MODE_B (string "WRITE_FIRST"))
      (property INIT_B (string "0"))
      (property SRVAL_B (string "0"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
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   )
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    )
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   (net (rename N5 "doutb<0>")
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    )
   )
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   )
   (net (rename N110 "addrb<6>")
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      (portRef (member addrb 2))
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    )
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      (portRef (member addrb 3))
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   (net (rename N112 "addrb<4>")
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    (joined
      (portRef clka)
      (portRef CLKA (instanceRef B5))
    )
   )
   (net (rename N118 "clkb")
    (joined
      (portRef clkb)
      (portRef CLKB (instanceRef B5))
    )
   )
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    )
   )
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      (portRef enb)
      (portRef ENB (instanceRef B5))
    )
   )
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    (joined
      (portRef sinitb)
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    )
   )
   (net (rename N133 "wea")
    (joined
      (portRef wea)
      (portRef WEA (instanceRef B5))
    )
   )
))))
(design dint_ram (cellRef dint_ram (libraryRef test_lib))
  (property X_CORE_INFO (string "blkmemdp_v5_0, Coregen 6.1.03i_ip1.01"))
  (property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)