dint_ram2.edn

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2005 10 4 20 9 33)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1.03i; Cores Update # 1.01"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_qualify_we = false ")
       (comment "c_mem_type = 2 ")
       (comment "c_has_qdpo_rst = true ")
       (comment "InstanceName = dint_ram2 ")
       (comment "c_has_qspo = true ")
       (comment "c_has_qspo_rst = false ")
       (comment "c_family = spartan3 ")
       (comment "c_has_dpo = false ")
       (comment "c_has_qdpo_clk = true ")
       (comment "c_has_d = true ")
       (comment "c_qce_joined = false ")
       (comment "c_width = 1 ")
       (comment "c_reg_a_d_inputs = false ")
       (comment "c_latency = 1 ")
       (comment "c_has_spo = false ")
       (comment "c_has_we = true ")
       (comment "c_depth = 32 ")
       (comment "c_has_i_ce = false ")
       (comment "c_default_data_radix = 1 ")
       (comment "c_default_data = 0 ")
       (comment "c_has_dpra = true ")
       (comment "c_has_clk = true ")
       (comment "c_enable_rlocs = true ")
       (comment "c_generate_mif = true ")
       (comment "c_has_qspo_ce = false ")
       (comment "c_addr_width = 5 ")
       (comment "c_has_qdpo_srst = false ")
       (comment "c_mux_type = 0 ")
       (comment "c_has_spra = false ")
       (comment "c_has_qdpo = true ")
       (comment "c_reg_dpra_input = false ")
       (comment "c_mem_init_file = dint_ram2.mif ")
       (comment "c_has_qspo_srst = false ")
       (comment "c_has_rd_en = false ")
       (comment "c_read_mif = false ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_qdpo_ce = false ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell RAM16X1D (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port WE (direction INPUT))
                   (port WCLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port DPRA0 (direction INPUT))
                   (port DPRA1 (direction INPUT))
                   (port DPRA2 (direction INPUT))
                   (port DPRA3 (direction INPUT))
                   (port SPO (direction OUTPUT))
                   (port DPO (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell dint_ram2
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename A "A<4:0>") 5 ) (direction INPUT))
   (port ( rename CLK "CLK") (direction INPUT))
   (port ( array ( rename D "D<0:0>") 1 ) (direction INPUT))
   (port ( rename WE "WE") (direction INPUT))
   (port ( array ( rename DPRA "DPRA<4:0>") 5 ) (direction INPUT))
   (port ( rename QDPO_CLK "QDPO_CLK") (direction INPUT))
   (port ( rename QDPO_RST "QDPO_RST") (direction INPUT))
   (port ( array ( rename QDPO "QDPO<0:0>") 1 ) (direction OUTPUT))
   (port ( array ( rename QSPO "QSPO<0:0>") 1 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU13
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y0"))
      (property INIT (string "4444"))
   )
   (instance BU18
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y0"))
      (property INIT (string "8888"))
   )
   (instance BU21
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property RLOC (string "x2y0"))
      (property INIT (string "0000"))
   )
   (instance BU26
      (viewRef view_1 (cellRef RAM16X1D (libraryRef xilinxun)))
      (property RLOC (string "x4y0"))
      (property INIT (string "0000"))
   )
   (instance BU37
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x6y0"))
      (property INIT (string "caca"))
   )
   (instance BU38
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "x6y0"))
   )
   (instance BU59
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x6y1"))
      (property INIT (string "caca"))
   )
   (instance BU60
      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
      (property RLOC (string "x6y1"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef I2 (instanceRef BU13))
      (portRef I3 (instanceRef BU13))
      (portRef I2 (instanceRef BU18))
      (portRef I3 (instanceRef BU18))
      (portRef I3 (instanceRef BU37))
      (portRef I3 (instanceRef BU59))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef CE (instanceRef BU38))
      (portRef CE (instanceRef BU60))
    )
   )
   (net (rename N2 "A<0>")
    (joined
      (portRef (member A 4))
      (portRef A0 (instanceRef BU21))
      (portRef A0 (instanceRef BU26))
    )
   )
   (net (rename N3 "A<1>")
    (joined
      (portRef (member A 3))
      (portRef A1 (instanceRef BU21))
      (portRef A1 (instanceRef BU26))
    )
   )
   (net (rename N4 "A<2>")
    (joined
      (portRef (member A 2))
      (portRef A2 (instanceRef BU21))
      (portRef A2 (instanceRef BU26))
    )
   )
   (net (rename N5 "A<3>")
    (joined
      (portRef (member A 1))
      (portRef A3 (instanceRef BU21))
      (portRef A3 (instanceRef BU26))
    )
   )
   (net (rename N6 "A<4>")
    (joined
      (portRef (member A 0))
      (portRef I0 (instanceRef BU13))
      (portRef I0 (instanceRef BU18))
      (portRef I2 (instanceRef BU37))
    )
   )
   (net (rename N7 "CLK")
    (joined
      (portRef CLK)
      (portRef WCLK (instanceRef BU21))
      (portRef WCLK (instanceRef BU26))
      (portRef C (instanceRef BU38))
    )
   )
   (net (rename N8 "D<0>")
    (joined
      (portRef (member D 0))
      (portRef D (instanceRef BU21))
      (portRef D (instanceRef BU26))
    )
   )
   (net (rename N9 "WE")
    (joined
      (portRef WE)
      (portRef I1 (instanceRef BU13))
      (portRef I1 (instanceRef BU18))
    )
   )
   (net (rename N10 "DPRA<0>")
    (joined
      (portRef (member DPRA 4))
      (portRef DPRA0 (instanceRef BU21))
      (portRef DPRA0 (instanceRef BU26))
    )
   )
   (net (rename N11 "DPRA<1>")
    (joined
      (portRef (member DPRA 3))
      (portRef DPRA1 (instanceRef BU21))
      (portRef DPRA1 (instanceRef BU26))
    )
   )
   (net (rename N12 "DPRA<2>")
    (joined
      (portRef (member DPRA 2))
      (portRef DPRA2 (instanceRef BU21))
      (portRef DPRA2 (instanceRef BU26))
    )
   )
   (net (rename N13 "DPRA<3>")
    (joined
      (portRef (member DPRA 1))
      (portRef DPRA3 (instanceRef BU21))
      (portRef DPRA3 (instanceRef BU26))
    )
   )
   (net (rename N14 "DPRA<4>")
    (joined
      (portRef (member DPRA 0))
      (portRef I2 (instanceRef BU59))
    )
   )
   (net (rename N15 "QDPO_CLK")
    (joined
      (portRef QDPO_CLK)
      (portRef C (instanceRef BU60))
    )
   )
   (net (rename N16 "QDPO<0>")
    (joined
      (portRef (member QDPO 0))
      (portRef Q (instanceRef BU60))
    )
   )
   (net (rename N17 "QSPO<0>")
    (joined
      (portRef (member QSPO 0))
      (portRef Q (instanceRef BU38))
    )
   )
   (net (rename N18 "QDPO_RST")
    (joined
      (portRef QDPO_RST)
      (portRef CLR (instanceRef BU60))
    )
   )
   (net N21
    (joined
      (portRef O (instanceRef BU13))
      (portRef WE (instanceRef BU21))
    )
   )
   (net N22
    (joined
      (portRef O (instanceRef BU18))
      (portRef WE (instanceRef BU26))
    )
   )
   (net N23
    (joined
      (portRef SPO (instanceRef BU21))
      (portRef I0 (instanceRef BU37))
    )
   )
   (net N24
    (joined
      (portRef DPO (instanceRef BU21))
      (portRef I0 (instanceRef BU59))
    )
   )
   (net N34
    (joined
      (portRef SPO (instanceRef BU26))
      (portRef I1 (instanceRef BU37))
    )
   )
   (net N35
    (joined
      (portRef DPO (instanceRef BU26))
      (portRef I1 (instanceRef BU59))
    )
   )
   (net N209
    (joined
      (portRef D (instanceRef BU38))
      (portRef O (instanceRef BU37))
    )
   )
   (net N254
    (joined
      (portRef D (instanceRef BU60))
      (portRef O (instanceRef BU59))
    )
   )
))))
(design dint_ram2 (cellRef dint_ram2 (libraryRef test_lib))
  (property X_CORE_INFO (string "C_DIST_MEM_V6_0, Coregen 6.1.03i_ip1.01"))
  (property PART (string "XC3S5000-4-fg900") (owner "Xilinx")))
)