change60_new.v

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

module change60(clk20M,clk60M,reset,inEn,outEn,dataInR,dataInI,dataOutR,dataOutI,FFT_set);
  input clk20M;
  input clk60M;
  input reset;
  input inEn;
  input [7:0]dataInR;
  input [7:0]dataInI;

  output outEn;
  output [7:0]dataOutR;
  output [7:0]dataOutI;	 
  output FFT_set;
  
  wire [7:0]dataOutR;
  wire [7:0]dataOutI;
  reg [7:0]dataInR_buf;
  reg [7:0]dataInI_buf;

  reg En;
  wire clk60M;
 


always @(posedge clk20M or negedge reset)
  begin
    if(!reset)
	  	begin
		  En<=0;
		  dataInR_buf<=0;
		  dataInI_buf<=0;

		end
	 else 
	   begin
	        if(inEn)
			    begin
				   dataInR_buf<=dataInR;
					dataInI_buf<=dataInI;		
					En<=1;					
				 end
			  else 
			    begin
			      dataInR_buf<=8'b0;
					dataInI_buf<=8'b0;
				   En<=0;
				 end
		end
  end

reg mode;
reg [5:0] k;

always @(posedge clk20M or negedge reset)
  begin
    if(!reset)
	   begin
	     k<=0;
		end
	 else begin
	       if(En) 
			   begin
			     if(k==63)
				    k<=0;
				  else
				    k<=k+1;  	  
				end
			end
	end
reg [7:0] r;
reg outEn;
reg FFT_set;
reg [5:0] t;

always @(posedge clk60M or negedge reset)
 begin
   if(!reset)
	  begin 
	    r<=0;
		 mode<=0;
		 FFT_set<=0;
		 outEn<=0;
	
	  end
	else begin
	       if(En)
			    begin
				   if(r==8'b10111010)
					       begin
							   FFT_set<=1;   // output FFT_set 6 clock cycle before dataOut 
								r<=r+1;
							 end
					else if(r==8'b10111100)	
					       begin
							   outEn<=1;   //output outEn 4 clock cycle before dataOut
								r<=r+1;
							 end
					else if(r==191)
					       begin
							   mode<=1;							
							   r<=0;
							 end
					else begin
					       r<=r+1;
							 FFT_set<=0;
							 outEn<=0;
						  end
				 end
			 else r<=0;
			 if(mode)
			    begin
			
	            if(t==63)
			         begin
						  t<=0;
						  mode<=0;
						end
			      else t<=t+1;
				 end
		  end
 end

 ramr ramr (    //BRAM for real part: input 20MHz, output 60MHz, depth 64 bytes
    .addra(k),
    .addrb(t),
    .clka(clk20M),
    .clkb(clk60M),
    .dina(dataInR_buf),
    .doutb(dataOutR),
    .enb(mode),
    .wea(En));

 rami rami (    //BRAM for image part: input 20MHz, output 60MHz, depth 64 bytes
    .addra(k),
    .addrb(t),
    .clka(clk20M),
    .clkb(clk60M),
    .dina(dataInI_buf),
    .doutb(dataOutI),
    .enb(mode),
    .wea(En));
endmodule