ramr.asy

来自「基于Xilinx+FPGA的OFDM通信系统基带设计-程序」· ASY 代码 · 共 40 行

Version 4
SymbolType BLOCK



RECTANGLE Normal 32 0 256 496
PIN 0 48  LEFT 36
PINATTR PinName addra[5:0]
PINATTR Polarity IN
LINE Wide 0 48 32 48
PIN 0 80  LEFT 36
PINATTR PinName dina[7:0]
PINATTR Polarity IN
LINE Wide 0 80 32 80
PIN 0 112  LEFT 36
PINATTR PinName wea
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 240  LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Normal 0 240 32 240
PIN 0 272  LEFT 36
PINATTR PinName addrb[5:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 368  LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Normal 0 368 32 368
PIN 0 464  LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Normal 0 464 32 464
PIN 288 272  RIGHT 36
PINATTR PinName doutb[7:0]
PINATTR Polarity OUT
LINE Wide 256 272 288 272
LINE Wide 256 272 288 272