bram1i.xco

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

# Xilinx CORE Generator 6.1.03i; Cores Update # 1.01
# Username = Administrator
# COREGenPath = D:\Xilinx\coregen
# ProjectPath = E:\jmj\CP_ADDER
# ExpandedProjectPath = E:\jmj\CP_ADDER
# OverwriteFiles = true
# Core name: bram1i
# Number of Primitives in design: 16
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 0
# Number of LUTs used in design: 0
# Number of REG used in design: 15
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 1
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Spartan3
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT Dual_Port_Block_Memory Spartan3 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port_a_additional_output_pipe_stages = 0
CSET port_b_active_clock_edge = Rising_Edge_Triggered
CSET port_a_enable_pin = false
CSET port_a_write_enable_polarity = Active_High
CSET port_a_initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET port_a_init_pin = false
CSET select_primitive = 16kx1
CSET port_b_enable_pin = true
CSET width_b = 8
CSET port_a_init_value = 0
CSET width_a = 8
CSET depth_b = 64
CSET port_a_register_inputs = true
CSET component_name = bram1i
CSET depth_a = 64
CSET configuration_port_b = Read_Only
CSET port_b_write_enable_polarity = Active_High
CSET configuration_port_a = Write_Only
CSET port_b_init_value = 0
CSET port_b_handshaking_pins = false
CSET port_b_register_inputs = false
CSET port_b_initialization_pin_polarity = Active_High
CSET load_init_file = false
CSET port_a_enable_pin_polarity = Active_High
CSET port_a_handshaking_pins = false
CSET port_b_additional_output_pipe_stages = 0
CSET port_b_enable_pin_polarity = Active_High
CSET port_b_init_pin = true
CSET write_mode_port_b = Read_After_Write
CSET write_mode_port_a = Read_After_Write
GENERATE