📄 addressspace.pas
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//////////////////////////////////////////////////////////////////////
// ARM7TDMI CPU basic cycle timings //////////////////////////////////
//////////////////////////////////////////////////////////////////////
// These are long past being needed, I only keep them around
// to tag different cycles in an equation as being of a particular
// type. Delphi is smart enough to constant fold out any of these,
// but it may be necessary on other compilers to do it manually.
cycI = 1; // No memory access cycle
cycS = 1; // Sequential memory access
cycN = 1; // Non sequential access
//////////////////////////////////////////////////////////////////////
// Condition codes ///////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
EQ = $0; // Equal
NE = $1; // Not equal
CS = $2; // Unsigned higher or same
CC = $3; // Unsigned lower
MI = $4; // Negative
PL = $5; // Positive or zero
VS = $6; // Overflow
VC = $7; // No overflow
HI = $8; // Unsigned higher
LS = $9; // Unsigned lower or same
GE = $A; // Greater or equal
LT = $B; // Less than
GT = $C; // Greater than
LE = $D; // Less than or equal
AL = $E; // Always
NV = $F; // Never, todo: is this depriciated on the arm7tdmi, or invalid
//////////////////////////////////////////////////////////////////////
// Barrel Shifter Codes //////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
LSL = 0; // Logical shift left
LSR = 1; // Logical shift right
ASR = 2; // Arithmatic shift right
ROR = 3; // Rotate right
//////////////////////////////////////////////////////////////////////
// Bits in the CPSR register /////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
SR_N = 2147483648; // 1 shl 31; fixme, why doesn't this work // negative
SR_Z = 1 shl 30; // zero
SR_C = 1 shl 29; // carry/borrow/extend
SR_V = 1 shl 28; // overflow
SR_I = 1 shl 7; // IRQ disable
SR_F = 1 shl 6; // FIQ disable
SR_T = 1 shl 5; // Thumb Mode if set
//////////////////////////////////////////////////////////////////////
SOUND_RESTART = 1 shl 15;
//////////////////////////////////////////////////////////////////////
// Instruction masks and signatures (currentOpcode and mask = sig) ///
//////////////////////////////////////////////////////////////////////
const
BX_MASK = $0FFFFFF0; // 0000 111111111111111111111111 0000
BX_SIG = $012FFF10; // 0000 000100101111111111110001 0000
ALU_SHIFT_BY_IMM_MASK = $0E000010; // 0000 111 0000 0 0000 0000 00000 00 1 0000
ALU_SHIFT_BY_IMM_SIG = $00000000; // 0000 000 0000 0 0000 0000 00000 00 0 0000
ALU_SHIFT_BY_REG_MASK = $0E000090; // 0000 111 0000 0 0000 0000 0000 1 00 1 0000
ALU_SHIFT_BY_REG_SIG = $00000010; // 0000 000 0000 0 0000 0000 0000 0 00 1 0000
ALU_IMM_ROT_MASK = $0E000000; // 0000 111 0000 0 0000 0000 0000 00000000
ALU_IMM_ROT_SIG = $02000000; // 0000 001 0000 0 0000 0000 0000 00000000
MULTIPLY_MASK = $0FC000F0; // 0000 111111 00 0000 0000 0000 1111 0000
MULTIPLY_SIG = $00000090; // 0000 000000 00 0000 0000 0000 1001 0000
MULTIPLY_LONG_MASK = $0F8000F0; // 0000 11111 000 0000 0000 0000 1111 0000
MULTIPLY_LONG_SIG = $00800090; // 0000 00001 000 0000 0000 0000 1001 0000
SINGLE_DATA_SWAP_MASK = $0FB00FF0; // 0000 11111 0 11 0000 0000 11111111 0000
SINGLE_DATA_SWAP_SIG = $01000090; // 0000 00010 0 00 0000 0000 00001001 0000
HW_XFER_REGOFS_MASK = $0E400F90; // 0000 111 00 1 00 0000 0000 11111 00 1 0000
HW_XFER_REGOFS_SIG = $00000090; // 0000 000 00 0 00 0000 0000 00001 00 1 0000
HW_XFER_IMMOFS_MASK = $0E400090; // 0000 111 00 1 00 0000 0000 0000 1 00 1 0000
HW_XFER_IMMOFS_SIG = $00400090; // 0000 000 00 1 00 0000 0000 0000 1 00 1 0000
SINGLE_DATA_XFER_MASK = $0C000000; // 0000 11 000000 0000 0000 000000000000
SINGLE_DATA_XFER_SIG = $04000000; // 0000 01 000000 0000 0000 000000000000
UNDEFINED_MASK = $0E000010; // 0000 111 00000 000000000000000 1 0000
UNDEFINED_SIG = $06000010; // 0000 011 00000 000000000000000 1 0000
BLOCK_DATA_XFER_MASK = $0E000000; // 0000 111 00000 0000 0000000000000000
BLOCK_DATA_XFER_SIG = $08000000; // 0000 100 00000 0000 0000000000000000
//
BRANCH_MASK = $0E000000; // 0000 111 0 000000000000000000000000
BRANCH_SIG = $0A000000; // 0000 101 0 000000000000000000000000
COPRO_DATA_XFER_MASK = $0E000000; // 0000 111 00000 0000 0000 0000 00000000
COPRO_DATA_XFER_SIG = $0C000000; // 0000 110 00000 0000 0000 0000 00000000
COPRO_DATA_OP_MASK = $0F000010; // 0000 1111 0000 0000 0000 0000 000 1 0000
COPRO_DATA_OP_SIG = $0E000000; // 0000 1110 0000 0000 0000 0000 000 0 0000
COPRO_REG_XFER_MASK = $0F000010; // 0000 1111 000 0 0000 0000 0000 000 1 0000
COPRO_REG_XFER_SIG = $0E000010; // 0000 1110 000 0 0000 0000 0000 000 1 0000
SWI_MASK = $0F000000; // 0000 1111 000000000000000000000000
SWI_SIG = $0F000000; // 0000 1111 000000000000000000000000
//////////////////////////////////////////////////////////////////////
// ALU Opcodes ///////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
AND_OPCODE = $0; // operand1 AND operand2
EOR_OPCODE = $1; // operand1 EOR operand2
SUB_OPCODE = $2; // operand1 - operand2
RSB_OPCODE = $3; // operand2 - operand1
ADD_OPCODE = $4; // operand1 + operand2
ADC_OPCODE = $5; // operand1 + operand2 + carry
SBC_OPCODE = $6; // operand1 - operand2 + carry - 1
RSC_OPCODE = $7; // operand2 - operand1 + carry - 1
TST_OPCODE = $8; // as AND, but result is not written
TEQ_OPCODE = $9; // as EOR, but result is not written
CMP_OPCODE = $A; // as SUB, but result is not written
CMN_OPCODE = $B; // as ADD, but result is not written
ORR_OPCODE = $C; // operand1 OR operand2
MOV_OPCODE = $D; // operand2 (operand1 is ignored)
BIC_OPCODE = $E; // operand1 AND NOT operand2 (Bit clear)
MVN_OPCODE = $F; // NOT operand2 (operand1 is ignored)
//////////////////////////////////////////////////////////////////////
type
TSoundChannel1 = record
enabled: boolean;
// freq is the number of ticks before waveIndex is incremented
freq: integer;
index: integer; // index is the freq counter
waveIndex: integer;
waveDuty: integer;
// If timed, then soundLength is the number of ticks before turning off
timed: boolean;
soundLength: integer;
volume: integer;
envIncrease: boolean;
// env rate is the number of ticks before the envelope is modified
envRate: integer;
envIndex: integer;
sweepDecrease: boolean;
sweepStep: integer;
// sweep rate is the number of ticks before the sweep is modified
sweepRate: integer;
sweepIndex: integer;
end;
TSoundChannel2 = record
enabled: boolean;
// freq is the number of ticks before waveIndex is incremented
freq: integer;
index: integer; // index is the freq counter
waveIndex: integer;
waveDuty: integer;
// If timed, then soundLength is the number of ticks before turning off
timed: boolean;
soundLength: integer;
volume: integer;
envIncrease: boolean;
// env rate is the number of ticks before the envelope is modified
envRate: integer;
envIndex: integer;
end;
TSoundChannel3 = record
enabled: boolean;
// freq is the number of ticks before waveIndex is incremented
freq: integer;
index: integer; // index is the freq counter
waveIndex: integer;
volume: integer;
doubleLength: boolean;
curBank: boolean;
backBank: array[0..15] of byte;
// If timed, then soundLength is the number of ticks before turning off
timed: boolean;
soundLength: integer;
end;
TSoundChannel4 = record
enabled: boolean;
index: integer; // index is the freq counter
freq: integer; // freq is the number of cycles before clocking the shift register
lfsr: integer;
use7steps: boolean; // controls whether the LFSR is 7 or 15 bits
// If timed, then soundLength is the number of ticks before turning off
timed: boolean;
soundLength: integer;
volume: integer;
envIncrease: boolean;
// env rate is the number of ticks before the envelope is modified
envRate: integer;
envIndex: integer;
end;
TDSoundRecord = record
writeIndex: integer;
fifo: array[0..31] of int8;
enabled: boolean;
lvol, rvol: integer;
timer: integer;
latched: int8;
end;
//////////////////////////////////////////////////////////////////////
TBreakpointMode = (bpmHard, bpmSoft);
TBreakpointModes = set of TBreakpointMode;
TvmOpaqueChunk = record
magic: array[0..7] of char;
version: uint32;
size: uint32;
end;
PvmOpaqueChunk = pointer;
TvmRegisterFile = record
regs: array[0..38] of uint32;
end;
TvmProfileToken = pointer; // totally opaque
TvmMemoryLock1 = record
version: uint16; // version number, should be 1
misc: uint16; // anything needed for the locking mechanism
bios: Puint8Array; // 16 KB
exwram: Puint8Array; // 256 KB
wram: Puint8Array; // 32 KB
iospace: Puint8Array; // 1 KB
palette: Puint8Array; // 1 KB
vram: Puint8Array; // 96 KB
oam: Puint8Array; // 1 KB
rom: Puint8Array; // specified by romsize
romsize: uint32;
reserved: array[0..23] of byte; // reserved
end;
//////////////////////////////////////////////////////////////////////
TvmOnSoundReady = procedure (data: pointer; length: integer);
TvmOnVideoReady = procedure (y: integer; sline: Puint16);
TvmOnConsoleReady = procedure (line: PChar);
TvmSavestate1 = record
magic: uint32;
version: integer;
size: integer;
crc: uint32;
cartLoaded: boolean;
filename: array[0..255] of char;
// Memory spaces
systemROM: array[0..SYSTEM_ROM_MASK] of byte; // 00000000h..00003FFFh
exWRAM: array[0..EX_WRAM_MASK] of byte; // 02000000h..0203FFFFh
WRAM: array[0..WRAM_MASK] of byte; // 03000000h..03007FFFh
registers: array[0..REGISTERS_MASK] of byte; // 04000000h..
palette: array[0..PALETTE_MASK] of byte; // 05000000h..050003FFh
VRAM: array[0..VRAM_MASK] of byte; // 06000000h..06017FFFh
OAM: array[0..OAM_MASK] of byte; // 07000000h..070003FFh
cartRAM: array[0..SRAM_MASK] of byte; // 0E000000h..
cartRAMdirty: boolean;
lastAddress: uint32;
// CPU status
cpuGlobalTicks: uint32;
cpuStopped, cpuHalted: boolean;
irqPending: boolean;
regs: array[0..36+2] of uint32;
SPSR: uint32;
// Events
HBlankEvent: integer;
enteringHBlank: boolean;
eventCycleDelta: integer;
eventCyclesLeft: integer;
// Sound
soundA, soundB: TDSoundRecord;
sound1: TSoundChannel1;
sound2: TSoundChannel2;
sound3: TSoundChannel3;
sound4: TSoundChannel4;
end;
PvmSavestate = ^TvmSavestate1;
//////////////////////////////////////////////////////////////////////
implementation ///////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
end.
//////////////////////////////////////////////////////////////////////
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