addressspace.pas

一个不出名的GBA模拟器

  SYSTEM_ROM_MASK = $3FFF;
  EX_WRAM_MASK = $3FFFF;
  WRAM_MASK = $7FFF;
  REGISTERS_MASK = $FFF;
  PALETTE_MASK = $3FF;
  VRAM_MASK = $1FFFF;
  OAM_MASK = $3FF;
  SRAM_MASK = $FFFF;
  EEPROM_MASK = $1FFF;

  // Wait State Control Register (R/W)
  //  [0..1]: Old cart bus speed ($0E000000 to $0FFFFFFF)
  //  [2..4]: AD mux bus speed ($08000000 to $09FFFFFF)
  //  [5..7]: AD mux bus speed ($0A000000 to $0BFFFFFF)
  //  [8..10]: AD mux bus speed ($0C000000 to $0DFFFFFF)
  //  [11..12]: Something to do with the PHI pin on the cart bus
  //  [13]: Unknown
  //  [14]: Enable the cart prefetch buffer
  //  [15]: I think this is the value of the switch in the cart slot (R)
  //        todo: test the switch theory and the PHI pin
  WAIT_STATE_CR = $204;
   WS_PREFETCH_BUFFER = 1 shl 14;
   WS_CART_SWITCH = 1 shl 15;

   // Waits for the AD mux cart bus (N, S bank 0, S bank 1, S bank 2)
   romWait: array[0..7, 0..3] of byte = (
     (4,2,4,8),(3,2,4,8),(2,2,4,8),(8,2,4,8),
     (4,1,1,1),(3,1,1,1),(2,1,1,1),(8,1,1,1));

   // Waits for the 8-bit cart bus (any type of access)
   sramWait: array[0..3] of byte = (4, 3, 2, 8);


//////////////////////////////////////////////////////////////////////
// Timers ////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

const
  // Timer control registers:
  //  [01]: Clock divider, fires every:
  //         00  1/1
  //         01  1/64
  //         10  1/256
  //         11  1/1024
  //  [2]: when set, the lower timer cascades into this one, for long term timers
  //  [6]: when set, trigger an IRQ on overflow
  //  [7]: when set, the timer is active
  // Timer value is a halfword counter
  TIMER0 =     $100; // Timer 0 value (16 bits)
  TIMER0_CR =  $102; // Timer 0 control (8 bits)
  TIMER1 =     $104; // Timer 1 value (16 bits)
  TIMER1_CR =  $106; // Timer 1 control (8 bits)
  TIMER2 =     $108; // Timer 2 value (16 bits)
  TIMER2_CR =  $10A; // Timer 2 control (8 bits)
  TIMER3 =     $10C; // Timer 3 value (16 bits)
  TIMER3_CR =  $10E; // Timer 3 control (8 bits)

  TIMER0_LATCH = $500;
  TIMER1_LATCH = $504;
  TIMER2_LATCH = $508;
  TIMER3_LATCH = $50C;

  TIMER0_CYCLES = $510;
  TIMER1_CYCLES = $514;
  TIMER2_CYCLES = $518;
  TIMER3_CYCLES = $51C;

  TIMER0_SPEED = $520;
  TIMER1_SPEED = $521;
  TIMER2_SPEED = $522;
  TIMER3_SPEED = $523;

  TIMER_ENABLED = 1 shl 7;
  TIMER_IRQ = 1 shl 6;
  TIMER_CASCADE = 1 shl 2;

//////////////////////////////////////////////////////////////////////
// DMA Registers /////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

  DMA0_SRC =   $B0; // 26 bit source address
  DMA0_DEST =  $B4; // 26 bit dest address
  DMA0_COUNT = $B8; // 14 bit word count
  DMA0_CR =    $BA; // control register
  DMA1_SRC =   $BC; // 26 bit source address
  DMA1_DEST =  $C0; // 26 bit dest address
  DMA1_COUNT = $C4; // 14 bit word count
  DMA1_CR =    $C6; // control register
  DMA2_SRC =   $C8; // 26 bit source address
  DMA2_DEST =  $CC; // 26 bit dest address
  DMA2_COUNT = $D0; // 14 bit word count
  DMA2_CR =    $D2; // control register
  DMA3_SRC =   $D4; // 26 bit source address
  DMA3_DEST =  $D8; // 26 bit dest address
  DMA3_COUNT = $DC; // 16 bit word count
  DMA3_CR =    $DE; // control register

  DMA_REPEAT = 1 shl 9;
  DMA_ENABLED = 1 shl 15;
  DMA_IRQ_REQ = 1 shl 14;

//////////////////////////////////////////////////////////////////////
// Joystick registers ////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

  // Key input register, clear when there is input
  //  [0]: A
  //  [1]: B
  //  [2]: Select
  //  [3]: Start
  //  [4]: D-pad right
  //  [5]: D-pad left
  //  [6]: D-pad up
  //  [7]: D-pad down
  //  [8]: Shoulder right
  //  [9]: Shoulder left
  KEYS =       $130; // Key status (10 bits)

  KEY_IRQ_ENABLED = $4000;
  KEY_IRQ_AND = $8000;     // if 1, KEYS and KEY_IRQ triggers, otherwise KEYS or KEY_IRQ
  KEY_IRQS = $132;         // Key irq mask in bottom 10

//////////////////////////////////////////////////////////////////////
// Sound Registers ///////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

const
  SOUNDA_FIFO = $0A0;      // 32 bit sound data for DSound A
  SOUNDB_FIFO = $0A4;      // 32 bit sound data for DSound B

  // Sound 1 is a square wave with sweep and envelope control
  SOUND1_SWEEP = $060;     // Sound 1 sweep control (8 bits)
    SOUND_SWEEP_DECREASE = 1 shl 3;  // 0: increase, 1: decrease

  SOUND1_LENGTH = $062;    // Sound 1 length control (8 bits)
  SOUND1_ENVELOPE = $063;  // Sound 1 envelope control (8 bits)
    SOUND_ENVELOPE_INCREASE = 1 shl 3; // 0: decrease, 1: increase

  SOUND1_FREQUENCY = $064; // Sound 1 frequency and control (16 bits)

  // Sound 2 is a square wave with envelope control
  SOUND2_LENGTH = $068;    // Sound 2 length control (8 bits)
  SOUND2_ENVELOPE = $069;  // Sound 2 envelope control (8 bits)
  SOUND2_FREQUENCY = $06C; // Sound 2 frequency and control (16 bits)

  // Sound 3 is a raw wave channel
  SOUND3_CR = $070;        // Sound 3 control register (8 bits)
   SOUND3_64SAMPLES = $20;
   SOUND3_BANK1 = $40;
   SOUND3_ACTIVE = $80;

  SOUND3_LENGTH = $072;    // Sound 3 length control (8 bits)
  SOUND3_VOLUME = $073;    // Sound 3 volume control (8 bits)
  SOUND3_FREQUENCY = $074; // Sound 3 frequency and control (8 bits)

  // Sound 4 is a white noise channel with envelope control
  SOUND4_LENGTH = $078;    // Sound 4 length control (8 bits)
  SOUND4_ENVELOPE = $079;  // Sound 4 envelope control (8 bits)
  SOUND4_CR = $07C;        // Sound 4 control register (16 bits)
  SOUND4_7_STEPS = $8;

  // Global sound control
  SOUND_VOLUME = $080;     // Controls the playing volumes of the channels (8 bits)
  SOUND_ACTIVE = $081;     // Controls how sounds are piped to the outputs (8 bits)
  SOUND_DSOUND_CR = $082;  // Sound A/B control register (16 bits)
  SOUND_ENABLED = $084;    // Top bit is master enable, low 4 are status bits (8 bits)
  SOUND_BIAS = $088;       // Unknown ??? (16 bits)

  SOUND3_PATTERN = $90;    // 16 bytes of 4 bit samples

  DSA_VOLUME_SH = 2;
  DSB_VOLUME_SH = 3;
  DSA_RIGHT = 1 shl 8;
  DSA_LEFT = 1 shl 9;
  DSA_TIMER = 1 shl 10;
  DSA_RESET = 1 shl 11;
  DSB_RIGHT = 1 shl 12;
  DSB_LEFT = 1 shl 13;
  DSB_TIMER = 1 shl 14;
  DSB_RESET = 1 shl 15;

//////////////////////////////////////////////////////////////////////
/// IRQ registers ////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

const
  // IRQ registers
  IRQ_ENABLED = $200;  // Bits for irq enabled as below
  IRQ_FLAGS =   $202;  // Bits for irq triggered as below
  IRQ_MASTER =  $208;  // Interrupt master enable

  PAUSE = $300;

  // Key irq control register ([0-9] are set when the
  // corresponding key might trigger an interrupt)
  // [14]: Key interrupt enable, the rest of the reg is ignored when cleared
  // [15]: clear = OR, set = AND.
  // An interrupt is only set if a key with the possibility bit is set, [14] is set,
  // and [15] is clear, or when all possibility bits are met, and [15] is set.
  // Capice.
  KEY_IRQ =    $132; // 16 bits

//////////////////////////////////////////////////////////////////////

const
  LAST_SWI = $2D;
  swiNames: array[$00..LAST_SWI] of string = (
  'SoftReset',
  'RegisterRAMReset',
  'Halt',
  'Stop',
  'IntrWait',
  'VBlankIntrWait',
  'Div',
  'DivARM',
  'Sqrt',
  'ArcTan',
  'ArcTan2',
  'CPUSet',
  'CPUFastSet',
  'BIOSChecksum',
  'BgAffineSet',
  'ObjAffineSet',
  'BitUnpack',
  'LZ77UncompRAM',
  'LZ77UncompVRAM',
  'HuffUncomp',
  'RLEUncompRAM',
  'RLEUncompVRAM',
  'Diff8bitUnfilterRAM',
  'Diff8bitUnfilterVRAM',
  'Diff16bitUnfilter',
  'SoundBiasChange',
  'SoundDriverInit',
  'SoundDriverMode',
  'SoundDriverMain',
  'SoundDriverVSync',
  'SoundChannelClear',
  'MIDIKey2Freq',
  'MusicPlayerOpen',
  'MusicPlayerStart',
  'MusicPlayerStop',
  'MusicPlayerContinue',
  'MusicPlayerFadeOut',
  'Multiboot',
  '<unknown $26>',
  '<unknown $27>',
  'SoundDriverVSyncOff',
  'SoundDriverVSyncOn',
  '<unknown $2A>',
  '<unknown $2B>',
  '<unknown $2C>',
  'BIOSBootSequence');

//////////////////////////////////////////////////////////////////////
// Interrupts ////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

const
  // IRQ flags
  IRQ_VBLANK =  $0001;
  IRQ_HBLANK =  $0002;
  IRQ_YLINE =   $0004;
  IRQ_TIMER0 =  $0008;
  IRQ_TIMER1 =  $0010;
  IRQ_TIMER2 =  $0020;
  IRQ_TIMER3 =  $0040;
  IRQ_NETWORK = $0080;
  IRQ_DMA0 =    $0100;
  IRQ_DMA1 =    $0200;
  IRQ_DMA2 =    $0400;
  IRQ_DMA3 =    $0800;
  IRQ_KEY =     $1000;
  IRQ_UNKNOWN = $2000;

//////////////////////////////////////////////////////////////////////
// Exception vectors /////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

  RESET_VECTOR = $00000000;           // Reset (Supervisor mode on entry)
  UNDEFINED_INST_VECTOR = $00000004;  // Undefined instruction (no mode change?)
  SWI_VECTOR = $00000008;             // Software interrupt (Supervisor mode on entry)
  ABORT_PREFETCH_VECTOR = $0000000C;  // Abort (prefetch) (Abort mode on entry)
  ABORT_DATA_VECTOR = $00000010;      // Abort (data) (Abort mode on entry)
  RESERVED_VECTOR = $00000014;        // Reserved
  IRQ_VECTOR = $00000018;             // IRQ (IRQ mode on entry)
  FIQ_VECTOR = $0000001C;             // FIQ (FIQ mode on entry)

//////////////////////////////////////////////////////////////////////
// Registers and shadows for other processor modes ///////////////////
//////////////////////////////////////////////////////////////////////

  R0 = 0;
  R1 = 1;
  R2 = 2;
  R3 = 3;
  R4 = 4;
  R5 = 5;
  R6 = 6;
  R7 = 7;
  R8 = 8;     R8_fiq = 17;
  R9 = 9;     R9_fiq = 18;
  R10 = 10;   R10_fiq = 19;
  R11 = 11;   R11_fiq = 20;
  R12 = 12;   R12_fiq = 21;
  R13 = 13;   R13_fiq = 22;   R13_svc = 25;   R13_abt = 28;   R13_irq = 31;   R13_und = 34;
  R14 = 14;   R14_fiq = 23;   R14_svc = 26;   R14_abt = 29;   R14_irq = 32;   R14_und = 35;
  R15 = 15;
  CPSR = 16;
              SPSR_fiq = 24;  SPSR_svc = 27;  SPSR_abt = 30;  SPSR_irq = 33;  SPSR_und = 36;
  LR = R14;
  PIPELINE_0 = 37;
  PIPELINE_1 = 38;

  // Modes                // Number of registers to swap
  MODE_USER =       $10;  // Shares regs with system
  MODE_FIQ =        $11;         FIQ_REGS = 7;
  MODE_IRQ =        $12;         IRQ_REGS = 2;
  MODE_SUPERVISOR = $13;  SUPERVISOR_REGS = 2;
  MODE_ABORT =      $17;       ABORT_REGS = 2;
  MODE_UNDEFINED =  $1B;   UNDEFINED_REGS = 2;
  MODE_SYSTEM =     $1F;  // Shares regs with user