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<TITLE>Mappy VM SDK - DMA</TITLE>
<META NAME="Author" CONTENT="Michael Noland">
<META NAME="Copyright" CONTENT="(C) 2001-2002 Bottled Light, Inc.">
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<BODY BGCOLOR="#FFFFFF" BACKGROUND="bgtile.jpg">

<H1>DMA Subsystem</H1>

<P>
Mappy VM has 4 DMA (direct memory access) channels which can normally copy memory faster than the CPU alone can.  DMA is not faster than the CPU when performing fills.  Each channel has a source and destination address, count, and control register.  The control register determines when the DMA transfer will occur, whether halfwords or words should be transferred, and how the addresses should be changed during the transfer.  There is a lot of flexibility, but DMA is typically just used to copy blocks of data from one part of memory to another.
</P>

<P>
The four channels have slightly different limitations, and are intended for different uses.  Since a DMA transfer can be initiated by other subsystems, there is a priority scheme in place for the transfers:
<UL>
<LI>Channel 0 is intended for precicley timed <A HREF="video.html#rasterfx">raster effects</A> and will interrupt any other channels, but cannot read from or write to cartridge spaces.</LI>
<LI>Channels 1 and 2 are intended to be used to refill the <A HREF="sound.html">sound FIFOs</A> when they are empty.</LI>
<LI>Channel 3 is intended for general purpose transfers and is typically started immediately by user code.  Its source and destination addresses are both specified in 28 bits, so it can access cartridge space in either direction.</LI>
</UL>
</P>

<H3>DMA does halt the CPU durring transfers</H3>
<P>
There is no possibility for the CPU to do other things during a transfer, although all other subsystems continues to operate.  The only snag is that an immediate DMA transfer starts 2 cycles after the enable bit is set, not instantly, so do not start multiple transfers on the same channel using back to back writes to the CR.  This is a rare situation, since seperate transfers would typically need writes to the address and count registers in between writes to the control register.
</P>


<HR><!------------------------------------------------------------------------->

<A NAME="dmaxsrc">
<H2>DMA Source Address Registers (<CODE>DMA<EM>x</EM>_SRC</CODE>)</H2>
<TABLE BORDER="1" SUMMARY="DMA Registers">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
	<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
	<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0B0</TD>
	<TD>DMA0_SRC_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 27 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0B2</TD>
	<TD>DMA0_SRC_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="11">High 11 of 27 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0BC</TD>
	<TD>DMA1_SRC_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 28 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0BE</TD>
	<TD>DMA1_SRC_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="4">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="12">High 12 of 28 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0C8</TD>
	<TD>DMA2_SRC_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 28 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0CA</TD>
	<TD>DMA2_SRC_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="4">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="12">High 12 of 28 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0D4</TD>
	<TD>DMA2_SRC_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 28 bit source address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0D6</TD>
	<TD>DMA2_SRC_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="4">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="12">High 12 of 28 bit source address</TD>
</TR>
</TABLE>

<H3>Details</H3>
<UL>
<LI>Write-only access to the source address for DMA transfers.  Channel 0 can only transfer from internal memory to internal memory, since it only has 27 bits to specify the source address.  The other three channels can also source from the cartridge space.</LI>
</UL>

<HR><!------------------------------------------------------------------------->

<A NAME="dmaxdest">
<H2>DMA Destination Address Registers (<CODE>DMA<EM>x</EM>_DEST</CODE>)</H2>
<TABLE BORDER="1" SUMMARY="DMA Registers">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
	<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
	<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0B4</TD>
	<TD>DMA0_DEST_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0B6</TD>
	<TD>DMA0_DEST_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="11">High 11 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0C0</TD>
	<TD>DMA1_DEST_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0C2</TD>
	<TD>DMA1_DEST_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="11">High 11 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0CC</TD>
	<TD>DMA2_DEST_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0CE</TD>
	<TD>DMA2_DEST_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="11">High 11 of 27 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0D8</TD>
	<TD>DMA3_DEST_L</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Low 16 of 28 bit destination address</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0DA</TD>
	<TD>DMA3_DEST_H</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="4">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="12">High 12 of 28 bit destination address</TD>
</TR>
</TABLE>

<H3>Details</H3>
<UL>
<LI>Write-only access to the destination address for DMA transfers.  Channel 3 can transfer to the cartridge space, but the other channels are limited to internal memory due to a 27 bit address.</LI>
</UL>

<HR><!------------------------------------------------------------------------->

<A NAME="dmaxcount">
<H2>DMA Count Registers (<CODE>DMA<EM>x</EM>_SIZE</CODE>)</H2>
<TABLE BORDER="1" SUMMARY="DMA Registers">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
	<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
	<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0B8</TD>
	<TD>DMA0_SIZE</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="2">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="14">Transfer Count</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0C4</TD>
	<TD>DMA1_SIZE</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="2">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="14">Transfer Count</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0D0</TD>
	<TD>DMA2_SIZE</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#000000" COLSPAN="2">&nbsp</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="14">Transfer Count</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0DC</TD>
	<TD>DMA3_SIZE</TD>
	<TD BGCOLOR="#FFC0C0">Write Only</TD>
	<TD BGCOLOR="#FFC0C0" COLSPAN="16">Transfer Count</TD>
</TR>
</TABLE>

<H3>Details</H3>
<UL>
<LI>Write-only access to the DMA transfer count.  This is in terms of the size specified in the DMA channel CR (either halfwords or words).</LI>
<LI>If zero is stored, the DMA channel will actually transfer the maximum size for that channel (16,384 transfers for channels 0 to 2, and 65,536 transfers for channel 3).  The value stored is not used when the a channel is set up for sound FIFO refills.</LI>
</UL>

<HR><!------------------------------------------------------------------------->

<A NAME="dmaxcr">
<H2>DMA Control Registers (<CODE>DMA<EM>x</EM>_CR</CODE>)</H2>
<TABLE BORDER="1" SUMMARY="DMA Registers">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
	<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
	<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0BA</TD>
	<TD>DMA0_CR</TD>
	<TD BGCOLOR="#C0FF70">Read Write</TD>
	<TD BGCOLOR="#C0FF70">Enabled</TD>
	<TD BGCOLOR="#C0FF70">IRQ</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Start Mode</TD>
	<TD BGCOLOR="#000000">&nbsp</TD>
	<TD BGCOLOR="#C0FF70">Width</TD>
	<TD BGCOLOR="#C0FF70">Repeat</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Source Mode</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Dest Mode</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0C6</TD>
	<TD>DMA1_CR</TD>
	<TD BGCOLOR="#C0FF70">Read Write</TD>
	<TD BGCOLOR="#C0FF70">Enabled</TD>
	<TD BGCOLOR="#C0FF70">IRQ</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Start Mode</TD>
	<TD BGCOLOR="#000000">&nbsp</TD>
	<TD BGCOLOR="#C0FF70">Width</TD>
	<TD BGCOLOR="#C0FF70">Repeat</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Source Mode</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Dest Mode</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0D2</TD>
	<TD>DMA2_CR</TD>
	<TD BGCOLOR="#C0FF70">Read Write</TD>
	<TD BGCOLOR="#C0FF70">Enabled</TD>
	<TD BGCOLOR="#C0FF70">IRQ</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Start Mode</TD>
	<TD BGCOLOR="#000000">&nbsp</TD>
	<TD BGCOLOR="#C0FF70">Width</TD>
	<TD BGCOLOR="#C0FF70">Repeat</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Source Mode</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Dest Mode</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
	<TD>$0DE</TD>
	<TD>DMA3_CR</TD>
	<TD BGCOLOR="#C0FF70">Read Write</TD>
	<TD BGCOLOR="#C0FF70">Enabled</TD>
	<TD BGCOLOR="#C0FF70">IRQ</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Start Mode</TD>
	<TD BGCOLOR="#000000">&nbsp;</TD>
	<TD BGCOLOR="#C0FF70">Width</TD>
	<TD BGCOLOR="#C0FF70">Repeat</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Source Mode</TD>
	<TD BGCOLOR="#C0FF70" COLSPAN="2">Dest Mode</TD>
	<TD BGCOLOR="#000000" COLSPAN="5">&nbsp</TD>
</TR>
</TABLE>


<H3>Details</H3>
<UL>
<LI>
 <STRONG>Bits 5-6</STRONG> define the <EM>destination address mode</EM> during transfers:
 <UL>
  <LI>00: Increment (<CODE>DMA_DEST_INC</CODE>)</LI>
  <LI>01: Decrement (<CODE>DMA_DEST_DEC</CODE>)</LI>
  <LI>10: Fixed (<CODE>DMA_DEST_FIXED</CODE>)</LI>
  <LI>11: Increment but restore after transfer (<CODE>DMA_DEST_INCREMENT_RELOAD</CODE>)</LI>
 </UL>
</LI>

<LI>
 <STRONG>Bits 7-8</STRONG> define the <EM>source address mode</EM> during transfers:
 <UL>
  <LI>00: Increment (<CODE>DMA_SRC_INC</CODE>)</LI>
  <LI>01: Decrement (<CODE>DMA_SRC_DEC</CODE>)</LI>
  <LI>10: Fixed (<CODE>DMA_SRC_FIXED</CODE>)</LI>
  <LI>11: <EM>Illegal</EM></LI>
 </UL>
</LI>

<LI><STRONG>Bit 9</STRONG> is the <EM>repeat enable</EM>.  When set, the DMA will keep occuring every time the start mode condition is met. The constant for this is <CODE>DMA_REPEAT</CODe>.</LI>
<LI><STRONG>Bit A</STRONG> controls the <EM>transfer width</EM>.  When cleared, each count represents one halfword (16 bits).  Otherwise, count is in terms of words (32 bits).  The constants for this are <CODE>DMA_16BIT</CODE> and <CODE>DMA_32BIT</CODE>.</LI>

<LI>
 <STRONG>Bits C-D</STRONG> control the <EM>start mode</EM>:
 <UL>
  <LI>00: Immediately (<STRONG>Warning:</STRONG> <EM>Transfer actually starts 2 cycles after the enable bit is set</EM>)  (<CODE>DMA_START_NOW</CODE>)</LI>
  <LI>01: V-Blank (<CODE>DMA_START_VBL</CODE>)</LI>
  <LI>10: H-Blank (<CODE>DMA_START_HBL</CODE>)</LI>
  <LI>11: Depends on the DMA channel: It is an <EM>illegal</EM> setting for channels 0 and 3, but specifies a transfer should occur when the sound FIFO needs refilling for channels 1 and 2 (<CODE>DMA_START_FIFO</CODE>).  For more information, see the <A HREF="sound.html">SDK documents</A> on sound.</LI>
 </UL>
</LI>

<LI><STRONG>Bit E</STRONG> is the local enable for the DMA completion <EM>IRQ</EM>, it must be set for an IRQ to be produced in addition to the corresponding bit in IE. The constant for this is <CODE>DMA_IRQ_ENABLE</CODE>.</LI>
<LI><STRONG>Bit F</STRONG> is the <EM>enable</EM> bit. The DMA channel is disabled when this bit is clear.  If the start mode is 0, the DMA transfer starts two cycles after this bit is set. The constant for this is <CODE>DMA_ENABLE</CODE>.</LI>

</UL>

<P>


<HR><!------------------------------------------------------------------------->

<P>
<H3>Uses and examples</H3>
<UL>
<LI>writeme fixme todo findme</LI>
</UL>
</P>

<BLOCKQUOTE>
<EM>Example: Transferring something or other.</EM>
<HR><TABLE BORDER="1" BGCOLOR="#FFFFFF"><TR><TD><PRE>

// fixme: write some code

</PRE></TD></TR></TABLE></BLOCKQUOTE>

<HR><!------------------------------------------------------------------------->

<P ALIGN="center">Copyright &copy; 2001 to 2002, Bottled Light, Inc.</P>

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