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<HEAD>
<TITLE>Mappy VM SDK - Memory Layout</TITLE>
<META NAME="Author" CONTENT="Michael Noland">
<META NAME="Copyright" CONTENT="(C) 2001-2002 Bottled Light, Inc.">
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<BODY BGCOLOR="#FFFFFF" BACKGROUND="bgtile.jpg">
<H1>Memory Layout</H1>
<A NAME="link">
<P>
Mappy VM has a number of different memory spaces, some of which are internal and fixed, while others vary in size and availability depending on the cartridge loaded.
</P>
<HR><!------------------------------------------------------------------------->
<H1>Memory Map</H1>
<TABLE BORDER="1" ALIGN="CENTER" CELLPADDING="4" CELLSPACING="0" SUMMARY="Memory Map" BGCOLOR="#FFD050">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>Description</TD>
<TD>Base</TD>
<TD>Size</TD>
<TD>Access Width</TD>
<TD>Wait States</TD>
<TD>Mirrors</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD>System ROM</TD>
<TD><CODE>0x00000000</CODE></TD>
<TD><CODE>0x4000</CODE></TD>
<TD>8/16/32</TD>
<TD>none</TD>
<TD> </TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD COLSPAN="6">Cannot be accessed by user code</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD>External RAM</TD>
<TD><CODE>0x02000000</CODE></TD>
<TD><CODE>0x40000</CODE></TD>
<TD>8/16/32</TD>
<TD>+2N/+2S</TD>
<TD>Mirrored from <CODE>0x02000000</CODE> to <CODE>0x02FFFFFF</CODE></TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD COLSPAN="6">This RAM is only external to the CPU, and is not actually on the cartridge</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD>Work RAM</TD>
<TD><CODE>0x03000000</CODE></TD>
<TD><CODE>0x8000</CODE></TD>
<TD>8/16/32</TD>
<TD>none</TD>
<TD>Mirrored from <CODE>0x03000000</CODE> to <CODE>0x03FFFFFF</CODE></TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD COLSPAN="6">This is the fastest RAM available, and is often used to store ARM code doing processor intensive tasks</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD>I/O Register Space</TD>
<TD><CODE>0x04000000</CODE></TD>
<TD>N/A</TD>
<TD>8/16/32</TD>
<TD>variable</TD>
<TD>fixme</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD COLSPAN="6">All system I/O is handled through these memory mapped registers</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD>Palette RAM</TD>
<TD><CODE>0x05000000</CODE></TD>
<TD><CODE>0x400</CODE></TD>
<TD>16/32</TD>
<TD>none</TD>
<TD>Mirrored from <CODE>0x05000000</CODE> to <CODE>0x05FFFFFF</CODE></TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD COLSPAN="6">Holds background and sprite palettes</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD>Video RAM</TD>
<TD><CODE>0x06000000</CODE></TD>
<TD><CODE>0x18000</CODE></TD>
<TD>16/32</TD>
<TD>Accesses may stall durring display</TD>
<TD>covered</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD COLSPAN="6">Contains all graphics and maps</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD>Sprite RAM (OAM)</TD>
<TD><CODE>0x07000000</CODE></TD>
<TD><CODE>0x400</CODE></TD>
<TD>16/32</TD>
<TD>Accesses will stall durring display</TD>
<TD>Mirrored from <CODE>0x07000000</CODE> to <CODE>0x07FFFFFF</CODE></TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD COLSPAN="6">Contains all sprite attributes</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD>Cartridge ROM</TD>
<TD><CODE>0x08000000</CODE></TD>
<TD>0..32 MB</TD>
<TD>8/16/32</TD>
<TD>variable</TD>
<TD>Mirrored from <CODE>0x08000000</CODE> to <CODE>0x0DFFFFFF</CODE> unless EEPROM is present
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD COLSPAN="6">All user code is initially held here</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD>Serial EEPROM</TD>
<TD><CODE>0x0D000000</CODE></TD>
<TD>4, 64 Kbit</TD>
<TD>8/16/32</TD>
<TD>variable</TD>
<TD>EEPROM when present is wired to A23 and D0, so it is mirrored across the top 16 MB of each ROM window</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#D0D0D0">
<TD COLSPAN="6">Some cartridges have either SRAM or flash ROM on board</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD>Cartridge RAM</TD>
<TD><CODE>0x0E000000</CODE></TD>
<TD>0..64 KB</TD>
<TD>8</TD>
<TD>variable</TD>
<TD>Mirrored from <CODE>0x0E000000</CODE> to <CODE>0x0FFFFFFF</CODE> when present in a cartridge</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#C0C0C0">
<TD COLSPAN="6">Some cartridges have either SRAM or flash ROM on board</TD>
</TR>
</TABLE>
<HR><!------------------------------------------------------------------------->
<P>
The system ROM contains a boot-up sequence, the <A HREF="cpu.html#exception">exception</A> vectors, and a number of system utilities collectivley called the BIOS (Basic Input/Output System).
The BIOS is banked out of memory when the PC is not within the BIOS itself, and so cannot be accessed by normal means. A BIOS function is executed using a <A HREF="bios.html#swi"><CODE>SWI</CODE></A> call with arguments in r0-r3.
</P>
<HR><!------------------------------------------------------------------------->
<P>
All memory contained on the cartridge has variable wait states controlled by the wait state register WS_CR. A wait state is an additional delay incurred durring a memory access because of the slower components used to save money. There are two types of memory access cycles, a N cycle, which is a non-sequential access and is typically longer than the other type, an S or sequential access. A sequential access is any one that follows the last memory access by 2 or 4 bytes. Both both N and S accesses cost one cycle from fast, internal memory. The wait states are listed as +N/+S and indicate the <EM>additional</EM> cycle penalty for each type of access. Thus a halfword read from external ram actually costs 3 cycles, not 1.
</P>
<A NAME="reg204">
<H2>Wait State Control Register (<CODE>WS_CR</CODE>)</H2>
<TABLE BORDER="1" SUMMARY="Wait State Control Register">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>$204</TD>
<TD>WS_CR</TD>
<TD BGCOLOR="#C0FF70">Read Write</TD>
<TD BGCOLOR="#D0D0D0">Cartridge Type (R)</TD>
<TD BGCOLOR="#C0FF70">Prefetch Enable</TD>
<TD BGCOLOR="#000000"> </TD>
<TD BGCOLOR="#C0FF70" COLSPAN="2">Cart Clock</TD>
<TD BGCOLOR="#C0FF70" COLSPAN="3">Bank 2</TD>
<TD BGCOLOR="#C0FF70" COLSPAN="3">Bank 1</TD>
<TD BGCOLOR="#C0FF70" COLSPAN="3">Bank 0</TD>
<TD BGCOLOR="#C0FF70" COLSPAN="2">SRAM mode</TD>
</TR>
</TABLE>
<P>
<H3>Details</H3>
<UL>
<LI> todo </LI>
</UL>
</P>
<HR><!------------------------------------------------------------------------->
<P ALIGN="center">Copyright © 2001 to 2002, Bottled Light, Inc.</P>
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