📄 interrupts.html
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<TITLE>Mappy VM SDK - Interrupts</TITLE>
<META NAME="Author" CONTENT="Michael Noland">
<META NAME="Copyright" CONTENT="(C) 2001-2002 Bottled Light, Inc.">
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<BODY BGCOLOR="#FFFFFF" BACKGROUND="bgtile.jpg">
<H1>Interrupts</H1>
<A NAME="irqs">
<P>
An interrupt is a mechanism for some other portion of Mappy VM to interrupt the current program flow, so the program can attend to what caused the interruption.
The main subsystems of Mappy VM (video hardware, DMA, timers, and networking) can generate interrupt requests (IRQs) if configured to do so. These IRQs are evaluated against the IME and IE registers explained below to set flags in the IF register and generate the IRQ input to the CPU.
For even more flexibility, the CPU itself can ignore IRQs indefinitely when the I bit in the <A HREF="cpu.html#cpsr">CPSR</A> is set.
</P>
<P>
Interrupts and other CPU <A HREF="cpu.html#exceptions">exceptions</A> force the CPU to resume execution at exception vectors that are within the <A HREF="memory.html#bios">BIOS</A>. Since the BIOS deals with the interrupt and the special conditions that the CPU requires to return from exceptions, writing an interrupt handler is simplified and can even be done purely in C or C++.
</P>
<P>
The BIOS handler loads an address from <CODE>0x03007FFC</CODE> and branches to it after preserving r0-r3, r12, and lr. This is the normal ARM calling convention, and your interrupt handler should return using a <CODE>BX LR</CODE>. After this, the BIOS restores the saved registers and returns to the previously interrupted code. There is a predefined macro INTR_ADDRESS to store the address of the user interrupt handler in <CODE>0x03007FFC</CODE>.
</P>
<P>
Thus, the order of events looks like:
<OL>
<LI>A subsystem completes its task (timer overflow, DMA transfer completes, etc...)</LI>
<LI>If the IRQ enabled bit is set in the subsystem CR, then the IRQ is checked against the IE and the IME</LI>
<LI>If the corresponding bit is set in IE, and IME is 1, IF is modified to indicate a valid IRQ.</LI>
<LI>Once this happens, the CPU will enter the BIOS IRQ handler as soon as the I bit in the CPSR is cleared</LI>
<LI>The CPU resumes execution at <CODE>0x18</CODE> in ARM mode, and the BIOS saves important registers</LI>
<LI>The user interrupt handler (pointed to by <CODE>0x03007FFC</CODE>) is called in ARM mode</LI>
<LI>The user interrupt handler returns to the BIOS with a standard <CODE>BX LR</CODE></LI>
<LI>The BIOS handler restores the saved registers and returns the CPU to executing the interrupted code</LI>
</OL>
</P>
<HR><!------------------------------------------------------------------------->
<A NAME="ime">
<H2>Master Interrupt Enable Register (IME)</H2>
<TABLE BORDER="1" SUMMARY="Master Interrupt Enable Register">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>$208</TD>
<TD>IME</TD>
<TD BGCOLOR="#C0FF70">Read Write</TD>
<TD BGCOLOR="#000000" COLSPAN="15"> </TD>
<TD BGCOLOR="#C0FF70">Enabled</TD>
</TR>
</TABLE>
<P>
<H3>Details</H3>
<UL><LI>Bit 0 controls the operation of all interrupts in Mappy VM.<UL>
<LI>When cleared, no interrupt requests are honored.</LI>
<LI>When set, the interrupt requests that are enabled in IE will occur.</LI>
</UL></LI>
</UL>
</P>
<HR><!------------------------------------------------------------------------->
<A NAME="ie">
<H2>Interrupt Enable Register (IE)</H2>
<TABLE BORDER="1" SUMMARY="Interrupt Enable Register">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>$200</TD>
<TD>IE</TD>
<TD BGCOLOR="#C0FF70">Read Write</TD>
<TD BGCOLOR="#000000" COLSPAN="2"> </TD>
<TD BGCOLOR="#C0FF70">Cartridge</TD>
<TD BGCOLOR="#C0FF70"><A HREF="joypad.html">Joypad</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 3</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 2</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 1</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 0</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="networking.html">Network</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 3</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 2</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 1</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 0</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">Y-trigger</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">H-blank</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">V-blank</A></TD>
</TR>
</TABLE>
<P>
<H3>Details</H3>
<UL>
<LI>Each bit in IE controls whether an <A HREF="glossary.html#irq">IRQ</A> will trigger an interrupt, in combination with IME.</LI>
<LI>All of the possible interrupts also have a seperate enable bit in respective registers that governs the generation of IRQs.</LI>
<LI>The constants in order are: <CODE>IRQ_VBLANK, IRQ_HBLANK, IRQ_YTRIGGER, IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_NETWORK, IRQ_DMA0, IRQ_DMA1, IRQ_DMA2, IRQ_DMA3, IRQ_JOYPAD, and IRQ_CARTRIDGE</CODE></LI>
</UL>
</P>
<HR><!------------------------------------------------------------------------->
<A NAME="if">
<H2>Interrupt Flags Registers (IF)</H2>
<TABLE BORDER="1" SUMMARY="Interrupt Flag Register">
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>Offset</TD><TD>Name</TD><TD>Type</TD>
<TD>F</TD><TD>E</TD><TD>D</TD><TD>C</TD><TD>B</TD><TD>A</TD><TD>9</TD><TD>8</TD>
<TD>7</TD><TD>6</TD><TD>5</TD><TD>4</TD><TD>3</TD><TD>2</TD><TD>1</TD><TD>0</TD>
</TR>
<TR ALIGN="CENTER" BGCOLOR="#FFD050">
<TD>$202</TD>
<TD>IF</TD>
<TD BGCOLOR="#C0FF70">Read Write*</TD>
<TD BGCOLOR="#000000" COLSPAN="2"> </TD>
<TD BGCOLOR="#C0FF70">Cartridge</TD>
<TD BGCOLOR="#C0FF70"><A HREF="joypad.html">Joypad</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 3</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 2</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 1</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="dma.html">DMA 0</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="networking.html">Network</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 3</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 2</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 1</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="timers.html">Timer 0</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">Y-trigger</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">H-blank</A></TD>
<TD BGCOLOR="#C0FF70"><A HREF="video.html">V-blank</A></TD>
</TR>
</TABLE>
<EM><STRONG>*</STRONG> Writing to the IF register performs an XOR on the latched flags. To clear IF, write the current value back like so:</EM> <CODE>IF |= IF</CODE>
<P>
<H3>Details</H3>
<UL>
<LI>Each bit in IF indicates that an IRQ enabled with the corresponding bit in IE has occured.</LI>
<LI>The hardware never clears the IF register, this must be done by the user's interrupt handler writing back the bits that it has acknowledged (writing a zero will not alter the bit in IF, a 1 must be written to reset bits in IF).</LI>
</UL>
</P>
<P>
<H3>Uses and examples</H3>
<UL>
<LI>writeme fixme todo findme</LI>
</UL>
</P>
<BLOCKQUOTE>
<EM>Example: A very simple interrupt handler.</EM>
<HR><TABLE BORDER="1" BGCOLOR="#FFFFFF"><TR><TD><PRE>
void vblankHandler(void) {
dprintf("This code was called by an interrupt!\n");
// Clear the v-blank IRQ bit in IF
IF |= IRQ_VBLANK;
}
void configureInterrupts(void) {
DISP_SR |= DISP_SR_VBLANK_IRQ;
IE |= IRQ_VBLANK;
INTR_ADDRESS = vblankHandler;
IME = 1;
}
// Note that although the handler is called vblankHandler, there can only be
// one interrupt handler for all interrupts. You can determine which interrupts
// have occured by looking at the IF register.
</PRE></TD></TR></TABLE></BLOCKQUOTE>
<HR><!------------------------------------------------------------------------->
<P ALIGN="center">Copyright © 2001 to 2002, Bottled Light, Inc.</P>
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