fzdiv.vhd

来自「一种基于VHDL的uart算法的实现」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fzdiv is
port(clk:in std_logic;
      clk_out : out std_logic);
 end fzdiv;
 architecture behav of fzdiv is
 signal clk_flag: std_logic;
 begin
 process(clk)
 variable count : std_logic_vector(5 downto 0);
 begin
 if(clk'event and clk='1')then
    if(count<"111111") then count:=count+'1';
         elsif(count="111111") then clk_flag<=not(clk_flag);
                   count:="000000";
                    end if;
                      else null;
                         end if;
          clk_out<=clK_flag;
             end process;
               end behav;