hour24_12.v

来自「关于单片机设计的电子钟的程序及设计」· Verilog 代码 · 共 29 行

`timescale 1ns / 100ps
module Hour24_12(Hour24,Hour12,AM);
	input  [5:0]Hour24;
	output [4:0]Hour12;
	reg    [4:0]Hour12;
	output AM;
	reg	   AM;

	always @(Hour24)
		if(Hour24<6'h12)
			begin
				AM<=1;
				if(Hour24==6'h00) Hour12<=6'h12;
				else Hour12<=Hour24;
			end
		else 
			begin
				AM<=0;
				if(Hour24==6'h12)Hour12<=Hour24;
				else if(Hour24==6'h20 ||Hour24==6'h21)
					begin Hour12[4:4]<=4'h0;Hour12[3:0]<=Hour24[3:0]+4'h8;end
				else 
					begin 
						Hour12[3:0]<=Hour24[3:0]-2'h2;
						if(Hour24<6'h20) Hour12[4:4]<=4'h0;
						else Hour12[4:4]<=4'h1;
					end
			end
endmodule