maincontrol.v

来自「关于单片机设计的电子钟的程序及设计」· Verilog 代码 · 共 43 行

// ---------- Design Unit Header ---------- //
`timescale 1ns / 100ps

module MainControl (Clk100Hz,ModeKey,Reset,SetKey,Mode,SetSel) ;

// ------------ Port declarations --------- //
input Clk100Hz,ModeKey;
input Reset;
input SetKey;
output [1:0] Mode;
output [2:0] SetSel;

// ----------- Signal declarations -------- //
wire SelSelReset;
wire SetEN;
reg CounterEnd;

assign SetEN=Mode[1];
//assign SelSelReset = Reset & ~(ModeKey | (Mode[0]==0 & (&SetSel)));
//原来的办法容易产生毛刺
assign SelSelReset = Reset & ~ModeKey & CounterEnd;

always @(posedge Clk100Hz)
	CounterEnd=~(Mode[0]==0 & (SetSel==3'b111));
	
Counter #(2)U_Mode
(
	.CLK(ModeKey),
	.Counter(Mode[1:0]),
	.CLR(Reset),
	.CE(1'b1)
);

Counter #(3)U_SetSel
(
	.CLK(SetKey),
	.Counter(SetSel[2:0]),
	.CE(SetEN),
	.CLR(SelSelReset)
);

endmodule