alarm.v

来自「关于单片机设计的电子钟的程序及设计」· Verilog 代码 · 共 34 行

//模块：闹钟模块
//功能：当闹钟使能信号为高电平，到了设定时间时，输出铃声使能的高电平
//输入：当前时间（ClkDay,Hour,Min,Sec），设定时间（AHour,AMin,AAM）
//输出：铃声使能信号（Alarm）

`timescale 1ns / 100ps

module Alarm (
	AlarmEn,AlarmHourEn,
	Hour,Min,Sec,AHour,AMin,Clk4Hz,Clk1Hz,Clk1k,Clk512Hz,Buzzer);

	input AlarmEn,AlarmHourEn,Clk4Hz,Clk1Hz,Clk1k,Clk512Hz;
	input [5:0] Hour,AHour ;
	input [6:0] Min,AMin ;
	input [6:0] Sec;
	output Buzzer;
	wire  AlarmOn,HourAlarmOn,AlarmStyle;

	assign AlarmOn=(AlarmEn && Hour==AHour && Min==AMin && Sec<7'h15)?1:0;
	assign HourAlarmOn=(Min==7'h59 && Sec[6:4]==3'h5 && AlarmHourEn)?1:0; 
	assign AlarmStyle=(Sec==7'h59)?(1):(0);	 //four short and one long Buzz	
	
	wire AlarmRingMask=Clk4Hz & Clk1Hz;//1010_0000
	wire HourRingMask=Sec[0];

	
	wire BuzzerMask=(AlarmOn)?AlarmRingMask:((HourAlarmOn)?HourRingMask :0) ;
	wire Frequence=(AlarmOn)? Clk1k:
	((HourAlarmOn)?(AlarmStyle? Clk1k :Clk512Hz ):Clk512Hz) ;
	
	assign Buzzer=BuzzerMask & Frequence;

endmodule