📄 cm_pwm_buck_enable.mdl
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BlockType SignalConversion
OverrideOpt off
}
Block {
BlockType InitialCondition
Value "1"
SampleTime "-1"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Lookup
InputValues "[-4:5]"
OutputValues " rand(1,10)-0.5"
LookUpMeth "Interpolation-Extrapolation"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
LUTDesignTableMode "Redesign Table"
LUTDesignDataSource "Block Dialog"
LUTDesignFunctionName "sqrt(x)"
LUTDesignUseExistingBP on
LUTDesignRelError "0.01"
LUTDesignAbsError "1e-6"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "cm_pwm_buck_enable"
Location [13, 87, 1097, 667]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Sum
Name "Add"
Ports [2, 1]
Position [475, 507, 505, 538]
Orientation "left"
NamePlacement "alternate"
Inputs "+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
SaturateOnIntegerOverflow off
}
Block {
BlockType Constant
Name "Constant"
Position [605, 500, 635, 530]
Orientation "left"
NamePlacement "alternate"
Value "1.2"
}
Block {
BlockType Constant
Name "Constant2"
Position [170, 415, 200, 445]
Value "4"
}
Block {
BlockType Reference
Name "Current Measurement"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [490, 98, 515, 122]
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "DC Voltage Source"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [160, 160, 180, 195]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Source"
SourceType "DC Voltage Source"
ShowPortLabels on
Amplitude "3.6"
Measurements "None"
}
Block {
BlockType Reference
Name "Diode"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [380, 140, 420, 195]
Orientation "up"
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "1"
Lon "0"
Vf "0.25"
IC "0"
Rs "500"
Cs "250e-9"
Measurements off
}
Block {
BlockType Gain
Name "Gain"
Position [425, 510, 455, 540]
Orientation "left"
NamePlacement "alternate"
Gain "5e2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain1"
Position [595, 270, 625, 300]
Orientation "down"
NamePlacement "alternate"
Gain "60"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Reference
Name "Ground"
Ports [0, 0, 0, 0, 0, 1]
Position [159, 355, 181, 380]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground1"
Ports [0, 0, 0, 0, 0, 1]
Position [389, 220, 411, 245]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground2"
Ports [0, 0, 0, 0, 0, 1]
Position [784, 280, 806, 305]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground3"
Ports [0, 0, 0, 0, 0, 1]
Position [744, 355, 766, 380]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [492, 250, 523, 280]
Orientation "up"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Reference
Name "Mosfet"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [300, 90, 355, 130]
NamePlacement "alternate"
SourceBlock "powerlib/Power\nElectronics/Mosfet"
SourceType "Mosfet"
ShowPortLabels on
Ron "0.001"
Lon "1e-6"
Rd ".001"
Vfd "0"
IC "0"
Rs "1e5"
Cs "inf"
Measurements off
}
Block {
BlockType Reference
Name "Parallel RLC Branch"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [769, 125, 821, 180]
Orientation "down"
NamePlacement "alternate"
AttributesFormatString "\\n"
SourceBlock "powerlib/Elements/Parallel RLC Branch"
SourceType "Parallel RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
RConnTagsString "__new0"
BranchType "RC"
Resistance "3"
Inductance "[]"
SetiL0 off
InitialCurrent "0"
Capacitance "10e-6"
Setx0 on
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "R1"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [741, 140, 769, 210]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "R"
Resistance "5e4"
Inductance "[]"
SetiL0 off
InitialCurrent "0"
Capacitance "[]"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType Reference
Name "R2"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [741, 250, 769, 320]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "R"
Resistance "1e5"
Inductance "[]"
SetiL0 off
InitialCurrent "0"
Capacitance "[]"
Setx0 off
InitialVoltage "0"
Measurements "None"
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator"
Position [392, 370, 423, 400]
Orientation "up"
InputSameDT off
LogicOutDataTypeMode "Boolean"
}
Block {
BlockType RelationalOperator
Name "Relational\nOperator1"
Position [250, 422, 280, 453]
InputSameDT off
LogicOutDataTypeMode "Boolean"
}
Block {
BlockType Reference
Name "Repeating\nSequence1"
Ports [0, 1]
Position [175, 470, 205, 500]
SourceBlock "simulink/Sources/Repeating\nSequence"
SourceType "Repeating table"
ShowPortLabels on
rep_seq_t "[0 0.8333e-6]"
rep_seq_y "[0 5]"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [940, 139, 970, 171]
Floating off
Location [6, 67, 1030, 761]
Open off
NumInputPorts "1"
ZoomMode "xonly"
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