log.v

来自「4位alu」· Verilog 代码 · 共 28 行

module log(a,b,S1,S0,h);
input [3:0] a,b;
input S1,S0;
output [3:0] h;


wire [3:0] a,b;
wire S1,S0;

reg [3:0] h;

always @(a or b or S1 or S0)
begin

case({S1,S0})
2'b00:  h=a&b;        //AND
2'b01:  h=a|b;        //OR
2'b10:  h=a^b;        //XOR
2'b11:  h=a^~b;       //XNOR
default: begin
$display("unknown opcode");
h=4'bxxxx;
end
endcase
end
endmodule