4_alu.v

来自「4位alu」· Verilog 代码 · 共 43 行

module alu(a,b,c0,S1,S0,M,f,cout);
input [3:0] a;
input [3:0] b;
input c0;

input S1,S0,M;
output [3:0] f;
output cout;

wire [3:0] a,b;
wire c0,S1,S0,M; 

wire [3:0] f;
wire cout;

wire [3:0] g,h;




log logic1(a,b,S1,S0,h);
arithmetic arithmetic1(a,b,c0,S1,S0,g,cout);

mux mux1(a,b,f,g,h,M);

endmodule