📄 arithmetic.v
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module arithmetic(a,b,c0,S1,S0,g,cout);input [3:0] a,b;input c0;input S1,S0;output [3:0] g;output cout;reg cout;wire [3:0] a,b;wire c0,S1,S0; reg [3:0] g;reg [4:0] result; // ALU result reg [3:0] ctl;always @(a or b or c0 or S1 or S0 )begin result = alu_out(a,b,c0,ctl); g = result[3:0]; cout = result[4] ; ctl= {S1,S0,c0}; endfunction [4:0] alu_out; input [3:0] a,b ; input c0 ; input [3:0] ctl ; begin case (ctl) 3'b000: alu_out=a; //Transfer 3'b001: alu_out=a+1; //Increase 3'b010: alu_out=a+b; //Addition 3'b011: alu_out=a+b+1; //Increment the sum of a and b by 1 3'b100: alu_out=a+(~b); //a plus one`s complement of b 3'b101: alu_out=a+(~b)+1; //a minus b 3'b110: alu_out=(~a)+b; //b plus one`s complement of a 3'b111: alu_out=(~a)+b+1; //b minus a default: begin $display("unknown opcode"); alu_out=5'bxxxxx; endendcaseendendfunction endmodule
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