📄 rtl81x9.h
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/* rtl81x9End.h - RealTek RTL81x9 Fast Ethernet interface header */
/* Copyright 1984-2000 Wind River Systems, Inc. */
/*
modification history
--------------------
01c,17feb00,dgy Added RTL_RSVD_INTERRUPTS for use to ensure that the
reserved interrupt bits are masked out prior to
interrupt status.
01b,26jan00,dgy Set the Early Rx Threshold within
the RTL_RXCFG_CONFIG
01a,29oct99,dgy written
*/
#ifndef __INCrtl81x9Endh
#define __INCrtl81x9Endh
#ifdef __cplusplus
extern "C" {
#endif
/***** DEBUG MACROS *****/
#define DRV_DEBUG
#ifdef DRV_DEBUG
#define RTL_DRV_DEBUG_OFF 0x0000
#define RTL_DRV_DEBUG_RX 0x0001
#define RTL_DRV_DEBUG_TX 0x0002
#define RTL_DRV_DEBUG_INT 0x0004
#define RTL_DRV_DEBUG_POLL_RX 0x0008
#define RTL_DRV_DEBUG_POLL_TX 0x0010
#define RTL_DRV_DEBUG_POLL (RTL_DRV_DEBUG_POLL_RX | RTL_DRV_DEBUG_POLL_TX)
#define RTL_DRV_DEBUG_LOAD 0x0020
#define RTL_DRV_DEBUG_IOCTL 0x0040
#define RTL_DRV_DEBUG_POLL_REDIR 0x10000
#define RTL_DRV_DEBUG_LOG_NVRAM 0x20000
#define RTL_DRV_DEBUG_ALL 0xfffff
#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \
if (rtl81x9Debug & FLG) \
logMsg(X0, X1, X2, X3, X4, X5, X6);
#define DRV_PRINT(FLG,X) \
if (rtl81x9Debug & FLG) logMsg X;
#else /*DRV_DEBUG*/
#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
#define DRV_PRINT(DBG_SW,X)
#endif /*DRV_DEBUG*/
/* DMA Definitions */
#define RTL_RXDMA_16BYTES 0x00000000
#define RTL_RXDMA_32BYTES 0x00000100
#define RTL_RXDMA_64BYTES 0x00000200
#define RTL_RXDMA_128BYTES 0x00000300
#define RTL_RXDMA_256BYTES 0x00000400
#define RTL_RXDMA_512BYTES 0x00000500
#define RTL_RXDMA_1024BYTES 0x00000600
#define RTL_RXDMA_UNLIMITED 0x00000700
#define RTL_RXFIFO_16BYTES 0x00000000
#define RTL_RXFIFO_32BYTES 0x00002000
#define RTL_RXFIFO_64BYTES 0x00004000
#define RTL_RXFIFO_128BYTES 0x00006000
#define RTL_RXFIFO_256BYTES 0x00008000
#define RTL_RXFIFO_512BYTES 0x0000A000
#define RTL_RXFIFO_1024BYTES 0x0000C000
#define RTL_RXFIFO_NOTHRESH 0x0000E000
#define RTL_TXDMA_16BYTES 0x00000000
#define RTL_TXDMA_32BYTES 0x00000100
#define RTL_TXDMA_64BYTES 0x00000200
#define RTL_TXDMA_128BYTES 0x00000300
#define RTL_TXDMA_256BYTES 0x00000400
#define RTL_TXDMA_512BYTES 0x00000500
#define RTL_TXDMA_1024BYTES 0x00000600
#define RTL_TXDMA_2048BYTES 0x00000700
/*
* The RealTek doesn't use a fragment-based descriptor mechanism.
* Instead, there are only four register sets, each or which represents
* one 'descriptor.' Basically, each TX descriptor is just a contiguous
* packet buffer (32-bit aligned!) and we place the buffer addresses in
* the registers so the chip knows where they are.
*
* For reception, there's just one large buffer where the chip stores
* all received packets.
*/
/* Configuration items */
#define RTL_BUFSIZ (ETHERMTU + ENET_HDR_REAL_SIZ + 6)
#define RTL_RMD_RLEN 5 /* ring size as a power of 2 -- 32 RMD's */
#define RTL_SPEED 10000000
/* Definitions for the drvCtrl flags field */
/* The format for the Flags field is as follows */
/* The first 16 bits are allocated as being used */
/* for miscellaneous flags. The second 16 bits */
/* are used for setting the Early Rx Threshold */
/* from within the string passed in initialisation */
/* This allows the user to taylor performance */
/* depending on their board without the need */
/* recomplile the driver source code. */
#define RTL_FLG_PROMISCUOUS_FLAG 0x01
#define RTL_FLG_MEM_ALLOC_FLAG 0x02
#define RTL_FLG_MODE_MEM_IO_MAP 0x04 /* device registers memory mapped */
#define RTL_FLG_POLLING 0x08 /* polling flag */
#define RTL_RXBUF_8 0x00000000
#define RTL_RXBUF_16 0x00000800
#define RTL_RXBUF_32 0x00001000
#define RTL_RXBUF_64 0x00001800
#define RTL_RX_BUF_SZ RTL_RXBUF_64
#define RTL_RXBUFLEN (1 << ((RTL_RX_BUF_SZ >> 11) + 13))
#define RTL_RX_FIFOTHRESH RTL_RXFIFO_NOTHRESH
#define RTL_RX_MAXDMA RTL_RXDMA_256BYTES
#define RTL_TX_MAXDMA RTL_TXDMA_256BYTES
/* configuration items */
#define RTL_DEV_NAME "rtl" /* device name */
#define RTL_DEV_NAME_LEN 4
#define RTL81x9_BUFSIZE 1536 /* aligned packet size */
#define RTL_CRC_SIZE 4
#define RTL_NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
/*
* Initialization Block.
* Specifies addresses of receive and transmit descriptor rings.
*/
typedef struct rtlIB
{
ULONG rtlIBMode; /* mode register */
UCHAR rtlIBPadr [8]; /* PADR: bswapd ethnt phys address */
UCHAR rtlIBLadrf [8]; /* logical address filter */
USHORT rtlIBRdraLow; /* RDRA: read ring lower address */
USHORT rtlIBRdraHigh; /* RDRA: read ring upper address */
} rtl_ib;
#define RTL_ADDR_TO_IB_RMD(addr, ib, rsize) \
ib->rtlIBRdraLow = (u_long) addr; \
ib->rtlIBRdraHigh = (((u_long) addr >> 16) & 0xff) | (rsize << 13);
/* Receive Message Descriptor Entry.*/
typedef struct rtlRxData
{
USHORT rxStatusFlags;
USHORT rxPktLen;
UCHAR *pktData;
} RTL_RX_DATA;
typedef struct rtlRMD
{
USHORT rxStatusFlags;
USHORT rxPktLen;
UCHAR *pktData;
} RTL_RMD;
/* clear the logical address filter */
#define RTL_ADDRF_CLEAR(pIb) (bzero(&(pIb)->rtlIBLadrf[0], 8))
/* set the logical address filter to accept a new multicast address */
#define RTL_ADDRF_SET(pIb, crc) \
(((pIb)->rtlIBLadrf[((crc) & 0x0000003f) >> 3]) |= (1 << ((crc) & 0x7)))
/* This driver supports the following four variants of the RTL Fast */
/* Ethernet Controller Chip. 8129, 8139 - Single Chip Fast */
/* Ethernet Controller. 8139A=8139 with power saving. 8139B=8139A + */
/* PCI/CardBus support */
#define RTL_DEV_8129 1
#define RTL_DEV_8139A 2
#define RTL_DEV_8139B 3
/*
* RealTek PCI vendor ID
*/
#define RTL_VENDORID 0x10EC
/*
* RealTek chip device IDs.
*/
#define RTL_DEVICEID_8129 0x8129
#define RTL_DEVICEID_8139 0x8139
/*
* Accton PCI vendor ID
*/
#define ACCTON_VENDORID 0x1113
/*
* Accton MPX 5030/5038 device ID.
*/
#define ACCTON_DEVICEID_5030 0x1211
/*
* Delta Electronics Vendor ID.
*/
#define DELTA_VENDORID 0x1500
/*
* Delta device IDs.
*/
#define DELTA_DEVICEID_8139 0x1360
/*
* Addtron vendor ID.
*/
#define ADDTRON_VENDORID 0x4033
/*
* Addtron device IDs.
*/
#define ADDTRON_DEVICEID_8139 0x1360
#if _BYTE_ORDER==_BIG_ENDIAN
#define PCI_SWAP(x) LONGSWAP((int)(x))
#define PCI_WORD_SWAP(x) ((LSB((USHORT)(x)) << 8) | MSB((USHORT)(x)))
#else
#define PCI_SWAP(x) (x)
#define PCI_WORD_SWAP(x) (x)
#endif
/*
* Generic shared memory read and write macros.
*/
#ifndef SHMEM_RD
# define SHMEM_RD(x) *(x)
#endif
#ifndef SHMEM_WR
# define SHMEM_WR(x,y) (*(x) = y)
#endif
/* RTL81x9 Registers */
#define RTL_REGS_IDR0 0x00
#define RTL_REGS_IDR1 0x01
#define RTL_REGS_IDR2 0x02
#define RTL_REGS_IDR3 0x03
#define RTL_REGS_IDR4 0x04
#define RTL_REGS_IDR5 0x05
#define RTL_REGS_MAR0 0x08 /* Multicast filter. */
#define RTL_REGS_TX_STATUS0 0x10
#define RTL_REGS_TX_STATUS1 0x14
#define RTL_REGS_TX_STATUS2 0x18
#define RTL_REGS_TX_STATUS3 0x1C
#define RTL_REGS_TX_ADDR0 0x20
#define RTL_REGS_TX_ADDR1 0x24
#define RTL_REGS_TX_ADDR2 0x28
#define RTL_REGS_TX_ADDR3 0x29
#define RTL_REGS_RX_BUF 0x30
#define RTL_REGS_RX_EARLY_CNT 0x34
#define RTL_REGS_RX_EARLY_STATUS 0x36
#define RTL_REGS_CHIP_CMD 0x37
#define RTL_REGS_RX_BUF_PTR 0x38
#define RTL_REGS_RX_BUF_ADDR 0x3A
#define RTL_REGS_INTR_MASK 0x3C
#define RTL_REGS_INTR_STATUS 0x3E
#define RTL_REGS_TX_CONFIG 0x40
#define RTL_REGS_RX_CONFIG 0x44
#define RTL_REGS_TIMER 0x48 /* A general-purpose counter. */
#define RTL_REGS_RX_MISSED 0x4C /* 24 bits valid, write clears. */
#define RTL_REGS_CFG_9346 0x50
#define RTL_REGS_CONFIG_0 0x51
#define RTL_REGS_CONFIG_1 0x52
#define RTL_REGS_TIMERINT 0x54
#define RTL_REGS_MSR 0x58
#define RTL_REGS_CONFIG3 0x59
#define RTL_REGS_MII 0x5A /* 8129 chip only */
#define RTL_REGS_MULTI_INTR 0x5C
#define RTL_REGS_PCI_RERID 0x5e
#define RTL_REGS_TX_SUMMARY 0x60
#define RTL_REGS_MII_BMCR 0x62
#define RTL_REGS_MII_BMSR 0x64
#define RTL_REGS_NWAY_ADVERT 0x66
#define RTL_REGS_NWAY_LPAR 0x68
#define RTL_REGS_NWAY_EXPANSION 0x6A
#define RTL_REGS_DIS 0x6c
#define RTL_REGS_FCSC 0x6e
#define RTL_REGS_NWAYTR 0x70 /* N-Way Test Register */
#define RTL_REGS_CSCR 0x74 /* Chip Status and Configuration Register. */
#define RTL_REGS_PARA_78 0x78
#define RTL_REGS_PARA_7c 0x7c /* Magic transceiver parameter register. */
/* Rx Status Bits - From Rx Packet Header */
#define RTL_RX_MULTICAST 0x8000
#define RTL_RX_PHYSICAL 0x4000
#define RTL_RX_BROADCAST 0x2000
#define RTL_RX_BAD_SYMBOL 0x0020
#define RTL_RX_RUNT 0x0010
#define RTL_RX_TOO_LONG 0x0008
#define RTL_RX_CRC_ERROR 0x0004
#define RTL_RX_BAD_ALIGN 0x0002
#define RTL_RX_STATUS_OK 0x0001
#define RTL_RX_UNFINISHED 0xfff0 /* DMA still in progress */
/* Tx Status Bits */
/* TSD0-3 - Offset 0010h - 001Fh - R/W */
#define RTL_TX_HOST_OWNS 0x2000
#define RTL_TX_UNDERRUN 0x4000
#define RTL_TX_STATUS_OK 0x8000
#define RTL_TX_OUT_OF_WINDOW 0x20000000
#define RTL_TX_ABORTED 0x40000000
#define RTL_TX_CARRIER_LOST 0x80000000
/* Chip Command Bits */
/* Offset 0037h - R/W */
#define RTL_CMD_RESET 0x10
#define RTL_CMD_RX_ENB 0x08
#define RTL_CMD_TX_ENB 0x04
#define RTL_CMD_RX_BUF_EMPTY 0x01
/* Interrupt Mask & Status register bits */
/* Mask - Offset 003Ch-003Dh - R/W */
/* Status - Offset 003Eh-003Fh - R/W */
#define RTL_IPT_PCI_ERR 0x8000
#define RTL_IPT_PCS_TIMEOUT 0x4000 /* 8129 only */
#define RTL_IPT_CABLE_LEN_CHG 0x2000
#define RTL_IPT_RX_FIFO_OVER 0x40 /* 8139 only */
#define RTL_IPT_RX_UNDERUN 0x20
#define RTL_IPT_RX_OVERFLOW 0x10
#define RTL_IPT_TX_ERR 0x08
#define RTL_IPT_TX_OK 0x04
#define RTL_IPT_RX_ERR 0x02
#define RTL_IPT_RX_OK 0x01
#define RTL_RSVD_INTERRUPTS 0x1f80 /* Reserved Interrupts */
#define RTL_VALID_INTERRUPTS 0xc07f /* All Interrupts above */
#define RTL_ERROR_INTERRUPTS 0x807a /* All bar OK's, TOUT and LEN_CHG */
#define RTL_RX_INTERRUPTS 0x73
#define RTL_TX_INTERRUPTS 0x0c
#define RTL_CONFIG_INTERRUPTS 0xe000 /* PCI,PCS,CABLE */
#define RTL_ALL_INTERRUPTS 0xffff
/* Transmit Config Regs */
/* Offset 0040-0043 */
#define RTL_TXCG_HWVER 0x80000000 /* 7 for RTL8139 (A and B) */
/* 6 for RTL8139 */
#define RTL_TXCG_BLID 0x40000000 /* DevType 0 - A 1 - B) */
#define RTL_TXCG_LBK1 0x40000 /* Loopback Test */
#define RTL_TXCG_LBK0 0x20000 /* 00 - Normal */
/* 01 - MAC */
/* 10 - PHY */
/* 11 - Twister */
#define RTL_TXCG_CRC 0x10000 /* Append CRC */
#define RTL_TXCG_MXDMA2 0x400 /* Max DMA Burst Size */
#define RTL_TXCG_MXDMA1 0x200 /* 000 - 16 001 - 32 */
#define RTL_TXCG_MXDMA0 0x100 /* 010 - 64 011 - 128 */
/* 100 - 256 101 - 512 */
/* 110 - 1024 111 - 2048 */
#define RTL_TXCG_TXRR 0x80 /* Retry Count - 16 * TXRR */
#define RTL_TXCG_CLRABT 0x01 /* Re transmit */
#define RTL_TXCG_MAXDMA 0x00000700 /* max DMA burst size */
#define RTL_TXCG_LOOPBKTST 0x00060000 /* loopback test */
#define RTL_TXCG_IFG 0x03000000 /* interframe gap */
/* Receive Configuration Register */
/* Offset 0044-0047h */
/* Note the Early Threshold bits are set by modifying the sysRtl81x9.c */
/* file stored within BSP directory. Altering the define RTL81X9_EARX_THRESH */
/* sets the Ealry threshold required in the passed endload string and then */
/* passed correctly into the configuration routine within the rtl81x9Start */
/* routine. */
#define RTL_RXCG_ERTH 0x40000 /* Early Rx Threshold Multiplier */
/* 0 - None 1 - 1/16 2 - 2/16 */
/* etc. etc. */
#define RTL_RXCG_MULERINT 0x20000 /* Multiple Early interrupt */
#define RTL_RXCG_RER8 0x10000 /* Rx Packet Length Error */
#define RTL_RXCG_RXFTH2 0x8000 /* Rx FIFO Threshold in Bytes */
#define RTL_RXCG_RXFTH1 0x4000 /* 000 - 16 , 001 - 32 */
#define RTL_RXCG_RXFTH0 0x2000 /* 010 - 64 , 011 - 128 */
/* 100 - 256 , 101 - 512 */
/* 110 - 1024 , 111 - none */
#define RTL_RXCG_RBLEN1 0x1000 /* Rx Buffer Length */
#define RTL_RXCG_RBLEN0 0x800 /* 00 - 8k + 16bytes */
/* 01 - 16k + 16bytes */
/* 10 - 32k + 16bytes */
/* 11 - 64k + 16bytes */
#define RTL_RXCG_MXDMA2 0x400 /* Max DMA Burst size per RX DMA */
#define RTL_RXCG_MXDMA1 0x200 /* 000 - 16 , 001 - 32 */
#define RTL_RXCG_MXDMA0 0x100 /* 010 - 64 , 011 - 128 */
/* 100 - 256 , 101 - 512 */
/* 110 - 1024 , 111 - unlimited */
#define RTL_RXCG_WRAP 0x80
#define RTL_RXCG_9356SEL 0x40 /* Selects EEPROM 1 - 9356 0 - 9346 */
#define RTL_RXCG_AER 0x20 /* Accept Error Packet */
#define RTL_RXCG_AR 0x10 /* Accept RUNT */
#define RTL_RXCG_AB 0x08 /* Accept Broadcast */
#define RTL_RXCG_AM 0x04 /* Accept Multicast */
#define RTL_RXCG_APM 0x02 /* Accept Physical match */
#define RTL_RXCG_AAP 0x01 /* Accept all Phy */
/* The following are used as the initial Tx and Rx Configs */
#define RTL_RXCFG_CONFIG (RTL_RX_BUF_SZ|RTL_RX_FIFOTHRESH|RTL_RX_MAXDMA)
#define RTL_TXCFG_CONFIG (RTL_TXCG_IFG|RTL_TX_MAXDMA)
/* 9346CR Command Register */
/* Offset 0050h - R/W */
#define RTL_EEMODE_PROGRAM 0x80 /* 8139B Operating Mode */
#define RTL_EEMODE_AUTOLOAD 0x40 /* 00 - Normal */
/* 01 - Auto Load */
/* 10 - 93c46 Prog Mode */
/* 11 - Cfg Reg Write Mode */
#define RTL_EEMODE_WRITECFG (0x80|0x40)
#define RTL_EEMODE_OFF 0x00
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