ln97xend.h

vxworks源码源码解读是学习vxworks的最佳途径

    UINT32      devAdrs;                /* device structure address */
    UINT16	csr3B;			/* csr3 value board specific */
    char *	pShMem;                 /* real ptr to shared memory */
    char *	memBase;                /* LANCE memory pool base */
    char *	memAdrs;                /* LANCE memory pool base */
    int         memSize;                /* LANCE memory pool size */
    int         memWidth;               /* width of data port */
    int         offset;			/* offset of data in the buffer */
    UINT32      flags;               	/* Our local flags */
    UINT32	pciMemBase;		/* memory base as seen from PCI*/
    UINT8	enetAddr[6];		/* ethernet address */
    CACHE_FUNCS cacheFuncs;             /* cache function pointers */
    BOOL        txBlocked;              /* transmit flow control */
    BOOL        txCleaning;		/* transmit descriptor cleaning */
    FUNCPTR     freeRtn [128];          /* Array of free routines. */
    FREE_ARGS   freeData [128];		/* Array of free arguments */
    CL_POOL_ID  pClPoolId;		/* cluster pool Id */
    M_CL_CONFIG	mClCfg;			/* mBlk & cluster config structure */
    CL_DESC	clDesc;			/* cluster descriptor table */
    END_ERR     lastError;              /* Last error passed to muxError */
    } LN_97X_DRV_CTRL;

/* Configuration items */

#define BUS_LATENCY_COUNT	0x1000	/* Max BUS timeo len in 0.1 uSeconds */
#define LN_MIN_FBUF    		100     /* Minsize of first buffer in chain */
#define LN_BUFSIZ		(ETHERMTU + ENET_HDR_REAL_SIZ + 6)
#define LN_SPEED        	10000000
#define LN_RMD_RLEN     	5       /* ring size as a ^ 2 -- 32 RMD's */
#define LN_TMD_TLEN     	5      	/* ring size as a ^ 2 -- 32 TMD's */
#define LN_RMD_MIN		2    	/* min descriptors 4 */
#define LN_TMD_MIN		2    	/* min descriptors 4 */
#define LN_RMD_MAX		7    	/* max descriptors 128 */
#define LN_TMD_MAX		7    	/* max descriptors 128 */
#define LN_97X_DEV_NAME 	"lnPci"	/* name of the device */
#define LN_97X_DEV_NAME_LEN 	6	/* length of the name string */
#define LN_97X_APROM_SIZE    	32	/* hardware address prom size */

/*
 * Generic shared memory read and write macros.
 */

#ifndef SHMEM_RD
#define SHMEM_RD(x)		*(x)
#endif

#ifndef SHMEM_WR
#define SHMEM_WR(x,y)		(*(x) = y)
#endif

#define LN_RMD_OWNED(rmd) 	(rmd->lnRMD1 & lnrmd1_OWN)

#define LN_PKT_LEN_GET(rmd) 	PCI_SWAP (rmd->rBufMskCnt) - 4;

/* device macros to read/write descriptor, initialization blocks, etc. */

#define LN_RMD_BUF_TO_ADDR(rmd, tmp, buf) \
	tmp = (void *)LN_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
	rmd->rBufAddr = (UINT32)PCI_SWAP (tmp);

#define LN_TMD_BUF_TO_ADDR(tmd, tmp, buf) \
	tmp = (void *)LN_CACHE_VIRT_TO_PHYS ((UINT32)buf); \
	tmp = (void *)MEM_TO_PCI_PHYS (tmp); \
        DRV_LOG (DRV_DEBUG_LOAD, "tBufAddr = 0x%X\n", tmp, 2, 3, 4, 5, 6); \
	tmd->tBufAddr = (ULONG)PCI_SWAP (tmp);

#define LN_TMD_TO_ADDR(tmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (tmd->rBufAddr)); \
        addr = LN_CACHE_PHYS_TO_VIRT(pTemp);		\
	}

#define LN_RMD_TO_ADDR(rmd, addr) \
	{	\
	UINT32 pTemp = PCI_TO_MEM_PHYS (PCI_SWAP (rmd->rBufAddr)); \
        addr = (char *)(LN_CACHE_PHYS_TO_VIRT(pTemp));		\
	}

#define LN_ADDR_TO_TMD(addr, tmd) \
	{	\
	UINT32 pTemp = LN_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	tmd->tBufAddr = PCI_SWAP (addr); \
	}

#define LN_ADDR_TO_RMD(addr, rmd) \
	{ \
	UINT32 pTemp = LN_CACHE_VIRT_TO_PHYS (buf);/* convert to phys addr */ \
        pTemp = (void *)(MEM_TO_PCI_PHYS((UINT32)pTemp));		\
	rmd->rBufAddr = PCI_SWAP (addr); \
	}

#define LN_CLEAN_TXD(tmd) \
	{ \
	UINT32 temp = TMD1_CNST | TMD1_ENP | TMD1_STP;	\
	tmd->tBufTmd2 = 0; 				\
        tmd->rbuf_tmd1 = PCI_SWAP (temp);		\
	}

#define LN_CLEAN_RXD(rmd) \
	{ \
	UINT32 temp;							\
	rmd->rBufMskCnt = 0; 						\
	temp = (RMD1_BCNT_MSK & -(LN_BUFSIZ)) | RMD1_OWN | RMD1_CNST | 	\
                                                RMD1_STP | RMD1_ENP;   	\
        rmd->rBufRmd1 = PCI_SWAP (temp);		               	\
	}

/* Set address of receiver descriptor ring and size in init block */

#define LN_ADDR_TO_IB_RMD(addr, ib, rsize) \
	{ \
        /* convert to phys addr */ \
	UINT32 pTemp = (UINT32)LN_CACHE_VIRT_TO_PHYS (addr);	\
        pTemp = (UINT32)MEM_TO_PCI_PHYS (pTemp);		\
	ib->lnIBRdra = PCI_SWAP (pTemp);			\
	pTemp = PCI_SWAP (ib->lnIBMode);			\
	pTemp |= IB_MODE_RLEN_MSK & (rsize << 20);		\
	ib->lnIBMode = PCI_SWAP (pTemp);			\
        DRV_LOG (DRV_DEBUG_LOAD, "IBmode = 0x%X Rdra = 0x%X\n", \
                 ib->lnIBMode, ib->lnIBRdra, 3, 4, 5, 6);       \
	}
	
/* Set address of transmitter descriptor ring and size in init block */

#define LN_ADDR_TO_IB_TMD(addr, ib, tsize) \
	{							\
        /* convert to phys addr */ 				\
        UINT32 pTemp = (UINT32)LN_CACHE_VIRT_TO_PHYS (addr);	\
        pTemp = (UINT32)MEM_TO_PCI_PHYS (pTemp);		\
	ib->lnIBTdra = PCI_SWAP (pTemp);			\
	pTemp = PCI_SWAP (ib->lnIBMode);			\
	pTemp |= IB_MODE_TLEN_MSK & (tsize << 28); 		\
	ib->lnIBMode = PCI_SWAP (pTemp);			\
        DRV_LOG (DRV_DEBUG_LOAD, "IBmode = 0x%X Tdra = 0x%X\n", \
                 ib->lnIBMode, ib->lnIBTdra, 3, 4, 5, 6); 	\
	}

/* clear the logical address filter */
    
#define LN_ADDRF_CLEAR(pIb) (bzero(&(pIb)->lnIBLadrf[0], 8))

/* set the logical address filter to accept a new multicast address */
    
#define LN_ADDRF_SET(pIb, crc) \
    (((pIb)->lnIBLadrf[((crc) & 0x0000003f) >> 3]) |= (1 << ((crc) & 0x7)))

#define LN_RMD_ERR(rmd) \
	(rmd->lnRMD1 & RMD1_ERR) || 		\
         ((rmd->lnRMD1 & (RMD1_STP | RMD1_ENP)) != (RMD1_STP | RMD1_ENP))

#define LN_TMD_CLR_ERR(tmd) \
        {		    \
	tmd->tBufTmd1 = 0; \
	tmd->tBufTmd2 = 0; \
        }

/* board level/bus specific and architecture specific macros */
    
#if _BYTE_ORDER==_BIG_ENDIAN
#   define PCI_SWAP(x)	LONGSWAP((int)(x))
#else
#   define PCI_SWAP(x)	(x)
#endif

#if (CPU_FAMILY==I80X86)

#ifndef SYS_OUT_LONG    
#define SYS_OUT_LONG(pDrvCtrl,addr,value) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        *((ULONG *)(addr)) = (value); 		\
    else 					\
        sysOutLong((int)(addr), (value)); 	\
    }
#endif /* SYS_OUT_LONG */

#ifndef SYS_IN_LONG    
#define SYS_IN_LONG(pDrvCtrl, addr, data) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        ((data) = *((ULONG *)(addr))); 		\
    else 					\
        ((data) = sysInLong((int) (addr))); 	\
    }
#endif /* SYS_IN_LONG */

#ifndef SYS_OUT_SHORT
#define SYS_OUT_SHORT(pDrvCtrl,addr,value) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        *((USHORT *)(addr)) = (value); 		\
    else 					\
        sysOutWord((int)(addr), (value)); 	\
    }
#endif /* SYS_OUT_SHORT */

#ifndef SYS_IN_SHORT
#define SYS_IN_SHORT(pDrvCtrl, addr, data) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        ((data) = *((USHORT *)(addr)));		\
    else 					\
        ((data) = sysInWord((int) (addr))); 	\
    }
#endif /* SYS_IN_SHORT */

#ifndef SYS_OUT_BYTE
#define SYS_OUT_BYTE(pDrvCtrl,addr,value) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        *((UCHAR *)(addr)) = (value); 		\
    else 					\
        sysOutByte((int)(addr), (value)); 	\
    }
#endif /* SYS_OUT_BYTE */

#ifndef SYS_IN_BYTE
#define SYS_IN_BYTE(pDrvCtrl, addr, data) \
    { \
    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP) 	\
        ((data) = *((UCHAR *)(addr))); 		\
    else 					\
        ((data) = sysInByte((int) (addr))); 	\
    }
#endif /* SYS_IN_BYTE */
#endif /* CPU_FAMILY == I80x86 */

#if defined(__STDC__) || defined(__cplusplus)
IMPORT END_OBJ * ln97xEndLoad (char * initString);
IMPORT STATUS 	 ln97xInitParse (LN_97X_DRV_CTRL * pDrvCtrl,char * initString);
#else
IMPORT END_OBJ * ln97xEndLoad ();
IMPORT STATUS	 ln97xInitParse ();
#endif  /* __STDC__ */

#endif  /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCln97xEndh */