iolicomend.h

vxworks源码源码解读是学习vxworks的最佳途径

 *
 * Those ever imaginative people at Intel have no other
 * names for the registers on their chip than r1, r2
 * etc..
 *
 */

#ifndef I82595_REGS_CONTIGUOUS
/*
 * To try and optimise I/O to the chip, this structure represents
 * the *real* appearance of the chip in the PID7T NISA I/O space;
 * the wierd wiring arrangement described in pid.h means that,
 * although the chip has a sequential collection of registers, they
 * appear to be grouped as two-register pairs, aligned on a word
 * boundary
 */
#define I595_R0		0x00
#define I595_R1		0x01
#define I595_R2		0x04
#define I595_R3		0x05
#define I595_R4		0x08
#define I595_R5		0x09
#define I595_R6		0x0C
#define I595_R7		0x0D
#define I595_R8		0x10
#define I595_R9		0x11
#define I595_R10	0x14
#define I595_R11	0x15
#define I595_R12	0x18
#define I595_R13	0x19
#define I595_R14	0x1C
#define I595_R15	0x1D
#else
/* Normal layout */
#define I595_R0		0x00
#define I595_R1		0x01
#define I595_R2		0x02
#define I595_R3		0x03
#define I595_R4		0x04
#define I595_R5		0x05
#define I595_R6		0x06
#define I595_R7		0x07
#define I595_R8		0x08
#define I595_R9		0x09
#define I595_R10	0x0A
#define I595_R11	0x0B
#define I595_R12	0x0C
#define I595_R13	0x0D
#define I595_R14	0x0E
#define I595_R15	0x0F
#endif /* !I82595_REGS_CONTIGUOUS */

/*
 * Register 0 is special, as it's the same in all banks
 * Access Macro to Register 0.
 */

#define SELECTBANK(c, b)(PCMCIA_IO_WRITE((c) + I595_R0, (b) << 6))
#define RUNCMD(c, o)	(PCMCIA_IO_WRITE((c) + I595_R0, \
                                                 ((o) & OPCODE_MASK)))
#define ABORTCMD(c)	(PCMCIA_IO_WRITE((c) + I595_R0, (1 << 5)))

/* 82595TX Command Set for register 0 */

#define CMD_MC_SETUP		0x03
#define CMD_TRANSMIT		0x04
#define CMD_TDR			0x05
#define CMD_DUMP		0x06
#define CMD_DIAGNOSE		0x07
#define CMD_RCV_ENABLE		0x08
#define CMD_RCV_DISABLE		0x0A
#define CMD_RCV_STOP		0x0B
#define CMD_ABORT		0x0D
#define CMD_RESET		0x0E
#define CMD_XMIT_RAW		0x14
#define CMD_CONT_XMIT_LIST	0x15
#define CMD_SET_TRISTATE	0x16
#define CMD_RESET_TRISTATE	0x17
#define CMD_POWER_DOWN		0x18
#define CMD_RESUME_XMIT_LIST	0x1C
#define CMD_SEL_RESET		0x1E

#define OPCODE_MASK		0x1F

/* 82595TX result codes for register 0 */

#define RESULT_INIT_DONE	0x0E

/* Definitions for fields and bits in the OLI_DEVICE */

/* I/O Bank 0 */

/* Reg 1 Interrupt/Status Register */

#define	BNK0_RX_SIT	0x01	/* RX stop interrupt */
#define	BNK0_RX_IT	0x02	/* RX interrupt */
#define	BNK0_TX_IT	0x04	/* TX interrupt */
#define	BNK0_EXE_IT	0x08	/* Execution interrupt */
#define	BNK0_EXE_IDL	0x00	/* Execution state idle */
#define	BNK0_EXE_BSY	0x20	/* Execution state busy */
#define	BNK0_EXE_ART	0x30	/* Execution state aborting */
#define	BNK0_RCV_DIS	0x00	/* Receive state disable */
#define	BNK0_RCV_RDY	0x40	/* Receive state ready */
#define	BNK0_RCV_ACT	0x80	/* Receive state active */
#define	BNK0_RCV_STP	0xC0	/* Receive state stopping */

#define BNK0_ITS_MSK	0x0F	/* All interrupts mask */
#define BNK0_EXE_MSK	0x30	/* Execution state mask */
#define BNK0_RCV_MSK	0xC0	/* Receive state mask */

#define BNK0_EXE_STE(r)	((r) & BNK0_EXE_MSK)
#define BNK0_RCV_STE(r)	((r) & BNK0_RCV_MSK)

/* Reg 3 Interrupt Mask Register */

#define BNK0_RX_SMK	0x01	/* RX stop interrupt mask */
#define	BNK0_RX_MK	0x02	/* RX interrupt mask */
#define	BNK0_TX_MK	0x04	/* TX interrupt mask */
#define	BNK0_EXE_MK	0x08	/* Execution interrupt mask */
#define BNK0_HAR_SLT	0x10	/* 32Bit IO port/host address select */
#define	BNK0_CBR_SLT	0x20	/* Current/Base register select */

/* I/O Bank 1 */

/* Reg 1 Config ISA Register/Tri-state irq lines */

#define	BNK1_ISA_HBW	0x02	/* Host bus width (ISA only) */
#define BNK1_ISA_ART	0x40	/* Alternate ready timing (ISA only) */
#define BNK1_TST_EN	0x80	/* Tri-state interrupt lines */

/* I/O Bank 2 */

/* Reg 1 Control the program features of the 82595TX */

#define	BNK2_TCP_DIS	0x01	/* Transmit concurrent processing disable */
#define	BNK2_PCM_ISA	0x10	/* PCMCIA/ISA Select */
#define	BNK2_TCH_END	0x20	/* Transmit chaining int mode */
#define	BNK2_TCH_ERR	0x40	/* Transmit chaining error stop */
#define	BNK2_BAD_DSC	0x80	/* Discard bad frames */

/* Reg 2 Control the program features of the 82595TX */

#define	BNK2_PCS_EN	0x01	/* Promiscous mode enable */
#define	BNK2_BRO_DIS	0x02	/* Disable broadcast */
#define	BNK2_RX_CRC	0x04	/* RX CRC in memory */
#define	BNK2_LEN_DIS	0x08	/* Length disable */
#define	BNK2_SAI_EN	0x10	/* enable source address insertion */
#define	BNK2_MIA_EN	0x20	/* Multi individual address enable */
#define	BNK2_LP_DIS	0x00	/* Loopback disable */
#define	BNK2_LP_INT	0x40	/* Internal loopback */
#define	BNK2_LP_EXT	0x80	/* External loopback */

/* Reg 3 Control the program features of the 82595TX */

#define BNK2_LI_DIS	0x01	/* Link integrity disable */
#define BNK2_PC_DIS	0x02	/* disable polarity correction */
#define BNK2_TPE_AUI	0x04	/* TPE/AUI */
#define BNK2_JB_DIS	0x08	/* Jabber disable */
#define BNK2_AP_EN	0x10	/* APORT */
#define BNK2_BNC_TPE	0x20	/* BNC/TPE */
#define	BNK2_TST_EN	0xC0	/* Production testing mode */


/* RCV status field*/

#define RCV_EOF		0x08	/* Reception of frame completed */
#define RCV_BOF		0x10	/* Begining of frame bit */
#define RCV_RXCPY	0x20	/* RCV copy threshold */
#define RCV_RECLM	0x40	/* RCV-DMA reclaimes location */
#define	RCV_UNDRN	0x80	/* RCV data underrun */

#define RCV_COL_DCT	0x0001	/* Collision detected */
#define RCV_IA_MCH	0x0002	/* Individual address match */
#define RCV_SRT_FRM	0x0080	/* Received frame shorter than 64Bytes */
#define RCV_OVR_RUN	0x0100	/* OVERRUN */
#define RCV_ALG_ERR	0x0400	/* Alignment error */
#define RCV_CRC_ERR	0x0800	/* CRC error */
#define RCV_LEN_ERR	0x1000	/* Length error */
#define RCV_OK		0x2000	/* Frame received OK */
#define RCV_TYP_LEN	0x8000	/* Type field */

/* XMT status field*/

#define XMT_COL_MAX	0x0020	/* Failed due to max collisions */
#define	XMT_HRT_BET	0x0040	/* Collision detect test passed after prev Tx */
#define	XMT_LN_DEF	0x0080	/* Tx deferred due to link activity */
#define	XMT_UND_RUN	0x0100	/* Underrun */
#define	XMT_LST_CRS	0x0400	/* Carrier sense lost */
#define	XMT_LT_COL	0x0800	/* Later collision */
#define	XMT_OK		0x2000	/* Transmit OK */
#define	XMT_COLL	0x8000	/* Collision on the last transmit */

#define	XMT_COL_MSK	0x000F	/* number collisions mask */
#define XMT_CHAIN	0x8000	/* Flag indicates a XMT chaining (16Bit) */
#define XMT_CHAIN_OCT	0x80	/* Flag indicates a XMT chaining (8Bit) */

#define TOTAL_RAM_SIZE	(64 * 1024)
#define RAM_TX_BASE	(0)
#define RAM_TX_SIZE	(32 * 1024)
#define RAM_TX_LIMIT	(RAM_TX_BASE + (RAM_TX_SIZE - 1))

#define RAM_RX_SIZE	(TOTAL_RAM_SIZE - RAM_TX_SIZE)
#define RAM_RX_BASE	(RAM_TX_SIZE)
#define RAM_RX_LIMIT	(RAM_RX_BASE + (RAM_RX_SIZE - 1))


/*
 * Macro for converting from packet byte count to length in Tx ring
 * buffer which needs to include 8 bytes of header and half-word
 * alignment
 */

#define COUNT_TO_LEN(x)	((x) + ((((x) & 0x01) == 0) ? 8 : 9))

/* Define Ethernet Network Driver parameters */

#define MAX_UNITS       1       /* max Olicom units */
#define DRV_NAME        "oli"
#define DRV_NAME_LEN    3
#define EADDR_LEN       6
#define OLI_BUFSIZ      (ETHERMTU + ENET_HDR_REAL_SIZ + EADDR_LEN)
#define OLI_SPEED       10000000

#define TX_BD_MIN       2       /* minimum number of Tx buffer descriptors */
#define TX_BD_MAX       0x14    /* maximum number of Tx buffer descriptors */
#define RX_BD_MIN       2       /* minimum number of Rx buffer descriptors */
#define TX_BD_DEFAULT   0x10    /* default number of Tx buffer descriptors */
#define RX_BD_DEFAULT   0x10    /* default number of Rx buffer descriptors */
#define OLI_MIN_FBUF    9       /* min. size of the first buffer in a frame */
#define OLI_MAX_XMT     0x600   /* max. size of the XMT block mem. structure */
#define NUM_LOAN        0x10    /* number of Rx loaner buffers in pool */

/* Define control structures */

/* typedefs */

typedef struct free_buf
    {
    void *      pClBuf;                 /* pointer cluster buffer */
    } FREE_BUF;

/* The definition of the driver control structure */

typedef struct end_device
    {
    END_OBJ     endObj;                 /* The class we inherit from. */
    int         unit;                   /* unit number */
    long        flags;                  /* Our local flags. */

    PCMCIA_CTRL pcmcia;                 /* PCMCIA control structure */
    int         ivec;                   /* interrupt vector */
    int         ilevel;                 /* interrupt level */

    int         txBdNum;                /* number of transmit BD */
    TX_BD *     txBdBase;               /* transmit BD base address */
    int         txBdNext;               /* next transmit BD to fill */
    int         txBdIndexC;             /* current transmit BD index */

    int         rxBdNum;                /* number of receive BD */
    RX_BD *     rxBdBase;               /* receive BD base address */
    int         rxBdNext;               /* next receive BD to read */

    char *      pShMem;                 /* real ptr to shared memory */
    ULONG       shMemSize;              /* shared memory size */

    UCHAR       enetAddr[EADDR_LEN];    /* ethernet address */
    int         offset;

    CACHE_FUNCS cacheFuncs;             /* cache function pointers */
    FREE_BUF    freeBuf[128];           /* Array of free routines. */
    CL_POOL_ID  clPoolId;
    } END_DEVICE;

#define FLTR_FRM_SIZE	0x180	/* filter frm size 64 Multicast address */

/* Definitions for the flags field */

#define OLI_RCV_HANDLING	0x0001
#define OLI_POLLING		0x0002	/* Poll mode */
#define OLI_TX_CLEANING		0x0004
#define OLI_TX_STOP		0x0008

#define OLI_MEMOWN		0x8000	/* memory allocated by driver */

/* state of transmit BD */

#define TX_BD_READY	0x80

/* state of receive BD */

#define RX_BD_EMPTY	0x01

/* definitions of several mask */

#define	OCT_MSK		0xFF	/* 8-bit mask */
#define	ODD_MSK		0x01	/* Odd mask */


#ifdef __cplusplus
}
#endif


#endif /* __INCiOlicomEndh */