iolicomend.h

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/* iOlicomEnd.h - END style Intel Olicom PCMCIA Ethernet interface header */

/* Copyright 1997-1998 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,02apr98,jpd  made conditionally-compilable version for Brutus and PID.
01b,16feb98.jpd  modified to work on Brutus, but not yet on both Brutus and PID.
01a,16dec97,rlp  copied from if_oli.h
*/

#ifndef __INCiOlicomEndh
#define __INCiOlicomEndh

#ifdef __cplusplus
extern "C" {
#endif

#include "end.h"
#include "netBufLib.h"

/* Define Constants */

#define PC_SOCKET_A             0x00
#define PC_SOCKET_B             0x40

#define ATTRIBUTE_MEMORY_SLOT   0x01000


#ifndef TARGET_HAS_NO_VADEM
#define PC_INDEX        ((volatile char *)(ctrlBase + 0x00))
#define PC_DATA_READ    ((volatile int *) (ctrlBase + 0x01))
#define PC_DATA_WRITE   ((volatile char *)(ctrlBase + 0x01))

#define MAPPED_MEMORY_BASE      0x10000         /* 64K */

#define ATTRIB_MEMORY_A         MAPPED_MEMORY_BASE
#define ATTRIB_MEMORY_B         ATTRIB_MEMORY_A + ATTRIBUTE_MEMORY_SLOT
#endif /* TARGET_HAS_NO_VADEM */

/*
 * Define to have complete control over the PCMCIA system.
 * These definitions are Access macro, I/O Registers, Control Registers,
 * PCMCIA Structures and Constants.
 */

/* Macro definition for PCMCIA Acces */

#ifndef I82595_REGS_CONTIGUOUS
#define PCMCIA_CALC_ADDR(x)     ((((x) & ~0x01) << 1) | ((x) & 0x01))

#define PCMCIA_READ_RAW(x, y)   (*(volatile UINT *) (PCMCIA_CALC_ADDR(x) | (y)))

#define PCMCIA_WRITE_RAW(x, y, z)       (*(volatile UCHAR *)    \
                                        (PCMCIA_CALC_ADDR(x) | (y)) = (z))

#define PCMCIA_IO_WRITE(x, y)   ((*(volatile UCHAR *)(x)) = (y))

#define PCMCIA_IO_READ(x)       ((((x) & 0x01) == 0) ?             \
                                (*(volatile UINT *)(x)) & OCT_MSK: \
                                (*(volatile UINT *)(x)) >> 24)

#define PCMCIA_ATTR_READ(x)	((((x) & ODD_MSK) == 0) ?  \
                PCMCIA_READ_RAW(x, (int)pDrvCtrl->pcmcia.memBaseA) & OCT_MSK :\
                PCMCIA_READ_RAW(x, (int)pDrvCtrl->pcmcia.memBaseA) >> 24)

#define PCMCIA_ATTR_WRITE(x, y)  PCMCIA_WRITE_RAW((x), (int)       \
                                        pDrvCtrl->pcmcia.memBaseA, (y))
/* On PID, two apparently registers cannot be read at once */

#define READ_R14_R15(val) \
    { \
    val =  PCMCIA_IO_READ((int)pDrvCtrl->pcmcia.oliAddr + I595_R14); \
    val |= (PCMCIA_IO_READ((int)pDrvCtrl->pcmcia.oliAddr + I595_R15) << 8); \
    }
#define READ_PTR_R14_R15(ptr) \
    { \
    *((UINT8 *)ptr)++ = \
	PCMCIA_IO_READ((int)pDrvCtrl->pcmcia.oliAddr + I595_R14); \
    *((UINT8 *)ptr)++ = \
	PCMCIA_IO_READ((int)pDrvCtrl->pcmcia.oliAddr + I595_R15); \
    }
#define WRITE_R14_R15(val) \
    { \
    PCMCIA_IO_WRITE((int)(pDrvCtrl->pcmcia.oliAddr + I595_R14), (val)); \
    PCMCIA_IO_WRITE((int)(pDrvCtrl->pcmcia.oliAddr + I595_R15), ((val) >> 8)); \
    }
#define WRITE_PTR_R14_R15(ptr) \
    { \
    PCMCIA_IO_WRITE((int)(pDrvCtrl->pcmcia.oliAddr + I595_R14), \
	*((UINT8 *)(ptr))++); \
    PCMCIA_IO_WRITE((int)(pDrvCtrl->pcmcia.oliAddr + I595_R15), \
	*((UINT8 *)(ptr))++); \
    }
#else
#define PCMCIA_CALC_ADDR(x)	(x)
#define PCMCIA_IO_WRITE(x, y)	((*(volatile UINT8 *) (x)) = (y))
#define PCMCIA_IO_WRITE16(x, y)	((*(volatile UINT16 *)(x)) = (y))
#define PCMCIA_IO_READ(x)	(* (volatile UINT8 *) (x))
#define PCMCIA_IO_READ16(x)	(* (volatile UINT16 *)(x))
#define PCMCIA_ATTR_READ(x)	(* (volatile UINT8 *) (x))
#define PCMCIA_ATTR_WRITE(x, y)	((*(volatile UINT8 *) (x)) = (y))

/* On Brutus, R14 and R15 can be read with one 16 bit operation */

#define READ_R14_R15(val) \
    { \
    val = (PCMCIA_IO_READ16 ((int)pDrvCtrl->pcmcia.oliAddr + I595_R14)); \
    }
#define READ_PTR_R14_R15(ptr) \
    { \
    *((UINT16 *)(ptr))++ = \
	(PCMCIA_IO_READ16 ((int)pDrvCtrl->pcmcia.oliAddr + I595_R14)); \
    }
#define WRITE_R14_R15(val) \
    PCMCIA_IO_WRITE16((UINT)(pDrvCtrl->pcmcia.oliAddr + I595_R14), (val));
#define WRITE_PTR_R14_R15(ptr) \
    PCMCIA_IO_WRITE16((UINT)(pDrvCtrl->pcmcia.oliAddr + I595_R14), \
	*((UINT16 *)(ptr))++);
#endif /* !I82595_REGS_CONTIGUOUS */
/* General Setup Registers */

#define PCIDREV		0x00	/* Identification & Revision */
#define PCIFSTATUS	0x01	/* Interface Status */
#define PCPWRRSTCTL	0x02	/* Power and RESETDRV Control */
#define PCCSTATCHNG	0x04	/* Card Status Change */
#define PCADDWINEN	0x06	/* Address Window Enable */
#define PCCDGCR		0x16	/* Card Detect and General Control Register */
#define PCGLBCTL	0x1E	/* Global Control Register */

#define PCINTGCTL	0x03	/* Interrupt & General Control */
#define PCSTATCHNGINT	0x05	/* Card Status Change Interrupt Configuration */

/* Definitions for fields in general setup registers */

/* Interface Status Register */

#define GSR_CD		0x0C	/* Card detect - Complement of CD[2:1] pins */
#define GSR_RDY		0x20	/* Card is ready */

/* Power and RESETDRV control register */

#define GSR_CPE		0x10	/* PC card power enable */
#define	GSR_PSE		0x20	/* Auto power switch enable */
#define	GSR_OE		0x80	/* Output enable */

/* Interrupt & general control register */

#define GSR_DRT		0x40	/* Deactivates reset signal to the PC card */

/* Card Status Change Register */

#define GSR_CDC		0x08	/* Card detect change */

/* Card status change interrupt configuration register */

#define GSR_IRQ4	0x40	/* IRQ4 enable */
#define GSR_IRQ3	0x30	/* IRQ3 enable */
#define GSR_CDE		0x08	/* Card detect enable */

/* Address window enable register */

#define GSR_WD0		0x01	/* Enable window 0 */

/* I/O Registers */

#define PCIOCTL	0x7	/* I/O Control */
#define PCIOA0STARTL	0x08	/* I/O Addr 0 Start Low */
#define PCIOA0STARTH	0x09	/* I/O Addr 0 Start High */
#define PCIOA0STOPL	0x0A	/* I/O Addr 0 Stop Low */
#define PCIOA0STOPH	0x0B	/* I/O Addr 0 Stop High */
#define PCIOA1STARTL	0x0C	/* I/O Addr 1 Start Low */
#define PCIOA1STARTH	0x0D	/* I/O Addr 1 Start High */
#define PCIOA1STOPL	0x0E	/* I/O Addr 1 Stop Low */
#define PCIOA1STOPH	0x0F	/* I/O Addr 1 Stop High */

#define PCSYSA0MSTARTL	0x10	/* System Memory Addr 0 Mapping Start Low */
#define PCSYSA0MSTARTH	0x11	/* System Memory Addr 0 Mapping Start High */
#define PCSYSA0MSTOPL	0x12	/* System Memory Addr 0 Mapping Stop Low */
#define PCSYSA0MSTOPH	0x13	/* System Memory Addr 0 Mapping Stop High */
#define PCCMEMA0OFFL	0x14	/* Card Memory Offset Addr 0 Low */
#define PCCMEMA0OFFH	0x15	/* Card Memory Offset Addr 0 High */

#define PCSYSA1MSTARTL	0x18	/* System Memory Addr 1 Mapping Start Low */
#define PCSYSA1MSTARTH	0x19	/* System Memory Addr 1 Mapping Start High */
#define PCSYSA1MSTOPL	0x1A	/* System Memory Addr 1 Mapping Stop Low */
#define PCSYSA1MSTOPH	0x1B	/* System Memory Addr 1 Mapping Stop High */
#define PCCMEMA1OFFL	0x1C	/* Card Memory Offset Addr 1 Low */
#define PCCMEMA1OFFH	0x1D	/* Card Memory Offset Addr 1 High */

#define PCSYSA2MSTARTL	0x20	/* System Memory Addr 2 Mapping Start Low */
#define PCSYSA2MSTARTH	0x21	/* System Memory Addr 2 Mapping Start High */
#define PCSYSA2MSTOPL	0x22	/* System Memory Addr 2 Mapping Stop Low */
#define PCSYSA2MSTOPH	0x23	/* System Memory Addr 2 Mapping Stop High */
#define PCCMEMA2OFFL	0x24	/* Card Memory Offset Addr 2 Low */
#define PCCMEMA2OFFH	0x25	/* Card Memory Offset Addr 2 High */

#define PCSYSA3MSTARTL	0x28	/* System Memory Addr 3 Mapping Start Low */
#define PCSYSA3MSTARTH	0x29	/* System Memory Addr 3 Mapping Start High */
#define PCSYSA3MSTOPL	0x2A	/* System Memory Addr 3 Mapping Stop Low */
#define PCSYSA3MSTOPH	0x2B	/* System Memory Addr 3 Mapping Stop High */
#define PCCMEMA3OFFL	0x2C	/* Card Memory Offset Addr 3 Low */
#define PCCMEMA3OFFH	0x2D	/* Card Memory Offset Addr 3 High */

#define PCSYSA4MSTARTL	0x30	/* System Memory Addr 4 Mapping Start Low */
#define PCSYSA4MSTARTH	0x31	/* System Memory Addr 4 Mapping Start High */
#define PCSYSA4MSTOPL	0x32	/* System Memory Addr 4 Mapping Stop Low */
#define PCSYSA4MSTOPH	0x33	/* System Memory Addr 4 Mapping Stop High */
#define PCCMEMA4OFFL	0x34	/* Card Memory Offset Addr 4 Low */
#define PCCMEMA4OFFH	0x35	/* Card Memory Offset Addr 4 High */

/* Unique Registers */

#define PCCONTROL	0x38	/* Control */
#define PCACTTIM	0x39	/* Activity Timer */
#define PCMISC		0x3A	/* Miscellaneous */
#define PCGPIOCON	0x3B	/* GPIO Configuration */
#define PCPROGCS	0x3D	/* Programmable Chip Select */
#define PCPROGCSCON	0x3E	/* Programmable Chip Select
				 * Configuration Register */
#define PCATA		0x3F	/* ATA */

/* Define PCMCIA structures */

typedef enum
    {
    COMMON,	/* Common memory */
    ATTRIBUTE	/* Attribute memory */
    }
    MEMTYPE;

typedef struct PCMCIASocket
{
    UINT	pcs_attrbase;
    UINT	pcs_attrrange;
    UINT	pcs_iobase;
    UINT	pcs_iorange;
} PCMCIASOCKET;

/* PCMCIA Control Structure */

typedef struct pcmcia_ctrl
    {
    char *		ioBaseA;	/* I/O space base address for Card A */
    char *		attrBaseA;	/* Attribute space base address Card A*/
    char *		memBaseA;	/* Memory space base address Card A */
    char *		ioBaseB;	/* I/O space base address for Card B */
    char *		attrBaseB;	/* Attribute space base address Card B*/
    char *		memBaseB;	/* Memory space base address Card B */
    char *		ctrlBase;	/* Base of Vadem PCMCIA controller */
    char *		oliAddr;	/* address of board */
    char *		oliAttribMem;	/* Address of attribute memory */
    int                 intLevelA;      /* Interrupt level for Card A */
    int                 intVectA;       /* Interrupt vector for Card A */
    int                 intLevelB;      /* Interrupt level for Card B */
    int                 intVectB;       /* Interrupt vector for Card B */
    BOOL                cardPresent;    /* TRUE if a card is in the slot */
    UINT		socket;         /* Socket holding card, A or B */
    PCMCIASOCKET        theSocket;      /* PCMCIA Socket descriptor */
    } PCMCIA_CTRL;

/* Trasmit Buffer Descriptor */

typedef struct tx_bd
    {
    UINT16              statusMode;     /* status and control */
    UINT16              dataLength;     /* length of data buffer in bytes */
    char *		dataPointer;    /* points to memory data buffer */
    } TX_BD;

/* Receive Buffer Descriptor */

typedef struct rx_bd
    {
    UINT16              statusMode;     /* status and control */
    UINT16              dataLength;     /* length of data buffer in bytes */
    char *		dataPointer;    /* points to memory data buffer */
    } RX_BD;

/* Olicom Card Configuration registers */

#define CARDCONFREG0	0x3F8
#define CARDCONFREG1	0x3FA

/* Definitions for fields in Olicom card configuration registers */

/* Register 1 */

#define CREG1_INT_IO	0x02	/* I/O Interrupt */

/* There are four tuples that we need to read from the card */

#define CARD_FUNCID	0x21	/* Should identify the card as
				   an Network Adaptor */
#define CARD_FUNCE	0x22	/* Function extension tuple detailing
				   the Ethernet hardware address */
#define	CARD_CONFIG	0x1A	/* Describes card configuration registers */
#define CARD_CFT_ENTRY	0x1B	/* There are several different copies of
				   this one tuple, which describe the
				   different I/O addresses accepted by the
				   Intel 82595 Controller */

/*
 * Register layout of the Intel 82595TX chip