intarchlib.c

vxworks源码源码解读是学习vxworks的最佳途径

*/

int intSRSet
    (
    int value	  /* value to write to status register */
    )

    {
    ...
    }

/*******************************************************************************
*
* intConnect - connect a C routine to a hardware interrupt
*
* This routine connects a specified C routine to a specified interrupt
* vector.  The address of <routine> is generally stored at <vector> so
* that <routine> is called with <parameter> when the interrupt occurs.
* The routine is invoked in supervisor mode at interrupt level.  A proper
* C environment is established, the necessary registers saved, and the
* stack set up.
*
* The routine can be any normal C code, except that it must not invoke
* certain operating system functions that may block or perform I/O
* operations.
*
* This routine generally simply calls intHandlerCreate() and
* intVecSet().  The address of the handler returned by intHandlerCreate()
* is what actually goes in the interrupt vector.
*
* This routine takes an interrupt vector as a parameter, which is the byte
* offset into the vector table. Macros are provided to convert between interrupt
* vectors and interrupt numbers, see `intArchLib'.
*
* NOTE ARM:
* ARM processors generally do not have on-chip interrupt controllers.
* Control of interrupts is a BSP-specific matter. This routine calls a
* BSP-specific routine to install the handler such that, when the
* interrupt occurs, <routine> is called with <parameter>.
*
* RETURNS: OK, or ERROR if the interrupt handler cannot be built.
*
* SEE ALSO: intHandlerCreate(), intVecSet()
*/

STATUS intConnect
    (
    VOIDFUNCPTR *  vector,      /* interrupt vector to attach to     */
    VOIDFUNCPTR    routine,     /* routine to be called              */
    int            parameter    /* parameter to be passed to routine */
    )

    {
    ...
    }


/*******************************************************************************
*
* intHandlerCreate - construct an interrupt handler for a C routine (MC680x0, SPARC, i960, x86, MIPS)
*
* This routine builds an interrupt handler around the specified C routine.
* This interrupt handler is then suitable for connecting to a specific
* vector address with intVecSet().  The interrupt handler is invoked in
* supervisor mode at interrupt level.  A proper C environment is
* established, the necessary registers saved, and the stack set up.
*
* The routine can be any normal C code, except that it must not invoke
* certain operating system functions that may block or perform I/O
* operations.
*
* RETURNS: A pointer to the new interrupt handler, or NULL if memory 
* is insufficient.
* 
*/

FUNCPTR intHandlerCreate
    (
    FUNCPTR  routine,     /* routine to be called              */
    int      parameter    /* parameter to be passed to routine */
    )

    {
    ...
    }

/*******************************************************************************
*
* intLockLevelSet - set the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)
* 
* This routine sets the current interrupt lock-out level and stores it
* in the globally accessible variable `intLockMask'.  The specified
* interrupt level is masked when interrupts are locked by
* intLock().  The default lock-out level (MC680x0 = 7, SPARC = 15,
* i960 = 31, i386/i486 = 1) is initially set by kernelInit() when
* VxWorks is initialized.
*
* NOTE ARM:
* On the ARM, this call establishes the interrupt level to be set when
* intLock() is called.
*
* RETURNS: N/A
* 
* SEE ALSO: intLockLevelGet(), intLock(), taskLock()
*/

void intLockLevelSet
    (
    int  newLevel        /* new interrupt level */
    )

    {
    ...
    }

/*******************************************************************************
*
* intLockLevelGet - get the current interrupt lock-out level (MC680x0, SPARC, i960, x86, ARM)
* 
* This routine returns the current interrupt lock-out level, which is
* set by intLockLevelSet() and stored in the globally accessible
* variable `intLockMask'.  This is the interrupt level currently
* masked when interrupts are locked out by intLock().  The default
* lock-out level (MC680x0 = 7, SPARC = 15, i960 = 31, i386/i486 = 1)
* is initially set by kernelInit() when VxWorks is initialized.
*
* RETURNS: The interrupt level currently stored in the interrupt
* lock-out mask. (ARM = ERROR always)
*
* SEE ALSO: intLockLevelSet()
*/

int intLockLevelGet (void)

    {
    ...
    }

/*******************************************************************************
*
* intVecBaseSet - set the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)
*
* This routine sets the vector (trap) base address.  The CPU's vector base
* register is set to the specified value, and subsequent calls to intVecGet()
* or intVecSet() will use this base address.  The vector base address is
* initially 0 (0x1000 for SPARC), until modified by calls to this routine.
*
* NOTE SPARC:
* On SPARC processors, the vector base address must be on a 4 Kbyte boundary
* (that is, its bottom 12 bits must be zero).
* 
* NOTE 68000:
* The 68000 has no vector base register; thus, this routine is a no-op for
* 68000 systems.
*
* NOTE I960:
* This routine is a no-op for i960 systems.  The interrupt vector table is
* located in sysLib, and moving it by intVecBaseSet() would require
* resetting the processor.  Also, the vector base is cached on-chip in the
* PRCB and thus cannot be set from this routine.
*
* NOTE MIPS:
* The MIPS processors have no vector base register;
* thus this routine is a no-op for this architecture.
*
* NOTE ARM:
* The ARM processors have no vector base register;
* thus this routine is a no-op for this architecture.
*
* RETURNS: N/A
*
* SEE ALSO: intVecBaseGet(), intVecGet(), intVecSet()
*/

void intVecBaseSet
    (
    FUNCPTR *  baseAddr     /* new vector (trap) base address */
    )

    {
    ...
    }

/*******************************************************************************
*
* intVecBaseGet - get the vector (trap) base address (MC680x0, SPARC, i960, x86, MIPS, ARM)
*
* This routine returns the current vector base address, which is set
* with intVecBaseSet().
*
* RETURNS: The current vector base address (i960 = value of `sysIntTable'
* set in sysLib, MIPS = 0 always, ARM = 0 always).
*
* SEE ALSO: intVecBaseSet()
*/

FUNCPTR *intVecBaseGet (void)

    {
    ...
    }

/******************************************************************************
*
* intVecSet - set a CPU vector (trap) (MC680x0, SPARC, i960, x86, MIPS)
*
* This routine attaches an exception/interrupt/trap handler to a specified 
* vector.  The vector is specified as an offset into the CPU's vector table. 
* This vector table starts, by default, at:
* 
* .TS
* tab(|);
* l l.
*     MC680x0:     | 0
*     SPARC:       | 0x1000
*     i960:        | `sysIntTable' in sysLib
*     MIPS:        | `excBsrTbl' in excArchLib
*     i386/i486:   | 0
* .TE
*
* However, the vector table may be set to start at any address with
* intVecBaseSet() (on CPUs for which it is available).  The vector table is
* set up in usrInit().
*
* This routine takes an interrupt vector as a parameter, which is the byte
* offset into the vector table. Macros are provided to convert between interrupt
* vectors and interrupt numbers, see `intArchLib'.
*
* NOTE SPARC:
* This routine generates code to:
* .IP (1) 4
* save volatile registers;
* .IP (2)
* fix possible window overflow;
* .IP (3)
* read the processor state register into register %L0; and 
* .IP (4)
* jump to the specified address.
* .LP
*
* The intVecSet() routine puts this generated code into the trap table
* entry corresponding to <vector>.
* 
* Window overflow and window underflow are sacred to
* the kernel and may not be pre-empted.  They are written here
* only to track changing trap base registers (TBRs).
* With the "branch anywhere" scheme (as opposed to the branch PC-relative
* +/-8 megabytes) the first instruction in the vector table must not be a 
* change of flow control nor affect any critical registers.  The JMPL that 
* replaces the BA will always execute the next vector's first instruction.
*
* NOTE I960:
* Vectors 0-7 are illegal vectors; using them puts the vector into the
* priorities/pending portion of the table, which yields undesirable
* actions.  The i960CA caches the NMI vector in internal RAM at system
* power-up.  This is where the vector is taken when the NMI occurs.  Thus, it
* is important to check to see if the vector being changed is the NMI
* vector, and, if so, to write it to internal RAM.
*
* NOTE MIPS:
* On MIPS CPUs the vector table is set up statically in software.
*
* RETURNS: N/A
*
* SEE ALSO: intVecBaseSet(), intVecGet()
*/

void intVecSet
    (
    FUNCPTR *	vector,		/* vector offset              */
    FUNCPTR	function	/* address to place in vector */
    )

    {
    ...
    }

/*******************************************************************************
*
* intVecGet - get an interrupt vector (MC680x0, SPARC, i960, x86, MIPS)
*
* This routine returns a pointer to the exception/interrupt handler attached
* to a specified vector.  The vector is specified as an offset into the CPU's
* vector table.  This vector table starts, by default, at:
* 
* .TS
* tab(|);
* l l.
*     MC680x0:     | 0
*     SPARC:       | 0x1000
*     i960:        | `sysIntTable' in sysLib
*     MIPS:        | `excBsrTbl' in excArchLib
*     i386/i486:   | 0
* .TE
*
* However, the vector table may be set to start at any address with
* intVecBaseSet() (on CPUs for which it is available).
*
* This routine takes an interrupt vector as a parameter, which is the byte
* offset into the vector table. Macros are provided to convert between interrupt
* vectors and interrupt numbers, see `intArchLib'.
*
* NOTE I960:
* The interrupt table location is reinitialized to <sysIntTable> after
* booting.  This location is returned by intVecBaseGet().
*
* RETURNS:
* A pointer to the exception/interrupt handler attached to the specified vector.
*
* SEE ALSO: intVecSet(), intVecBaseSet()
*/

FUNCPTR intVecGet
    (
    FUNCPTR *  vector     /* vector offset */
    )

    {
    ...
    }


/*******************************************************************************
*
* intVecTableWriteProtect - write-protect exception vector table (MC680x0, SPARC, i960, x86, ARM)
*
* If the unbundled Memory Management Unit (MMU) support package (VxVMI) is
* present, this routine write-protects the exception vector table to
* protect it from being accidentally corrupted.
*
* Note that other data structures contained in the page will also be 
* write-protected.  In the default VxWorks configuration, the exception vector
* table is located at location 0 in memory.  Write-protecting this affects
* the backplane anchor, boot configuration information, and potentially the
* text segment (assuming the default text location of 0x1000.)  All code
* that manipulates these structures has been modified to write-enable 
* memory for the duration of the operation.  If you select a different
* address for the exception vector table, be sure it resides in a page
* separate from other writable data structures.
*
* RETURNS: OK, or ERROR if memory cannot be write-protected.
*
* ERRNO: S_intLib_VEC_TABLE_WP_UNAVAILABLE
*/

STATUS intVecTableWriteProtect (void)

    {
    ...
    }


/********************************************************************************
* intUninitVecSet - set the uninitialized vector handler (ARM)
*
* This routine installs a handler for the uninitialized vectors to be
* called when any uninitialised vector is entered.
*
* RETURNS: N/A.
*/

void intUninitVecSet
    (
    VOIDFUNCPTR routine /* ptr to user routine */
    )

    {
    ...
    }