cachearchlib.c

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/* cacheArchLib.c - I80X86 cache management library */

/* Copyright 1984-1998 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01l,15feb99,hdn  added support for PentiumPro's bus snoop.
01k,09apr98,hdn  added support for PentiumPro.
01j,17jun96,hdn  stopped to use a return value of sysCpuProbe().
01i,21sep95,hdn  added support for NS486.
01h,01nov94,hdn  added a check of sysProcessor for Pentium
01g,27oct94,hdn  cleaned up.
01f,04oct94,hdn  added a checking and setting the cache mode.
01e,29may94,hdn  changed a macro I80486 to sysProcessor.
01d,05nov93,hdn  added cacheArchFlush().
01c,30jul93,hdn  added cacheArchDmaMalloc(), cacheArchDmaFree().
01b,27jul93,hdn  added cacheArchClearEntry().
01a,08jun93,hdn  written.
*/

/*
DESCRIPTION
This library contains architecture-specific cache library functions for
the Intel 80486 family caches.

INCLUDE FILES: cacheLib.h

SEE ALSO: cacheLib, vmLib

*/

/* LINTLIBRARY */

#include "vxWorks.h"
#include "errnoLib.h"
#include "cacheLib.h"
#include "stdlib.h"
#include "private/memPartLibP.h"
#include "private/vmLibP.h"
#include "private/funcBindP.h"
#include "regs.h"


/* externals */

IMPORT UINT sysProcessor;
IMPORT int sysCpuProbe (void);


/*******************************************************************************
*
* cacheArchLibInit - initialize the cache library
* 
* This routine initializes the cache library for Intel 80486
* processors.  The caching mode CACHE_WRITETHROUGH is available for the i86
* processor family.  It initializes the function pointers.
*
* RETURNS: OK.
*/

STATUS cacheArchLibInit
    (
    CACHE_MODE	instMode,	/* instruction cache mode */
    CACHE_MODE	dataMode	/* data cache mode */
    )
    {

    (void) sysCpuProbe ();			/* set a type of CPU */

    if ((sysProcessor == X86CPU_486) || (sysProcessor == X86CPU_PENTIUM) ||
	(sysProcessor == X86CPU_PENTIUMPRO))
	{
        cacheLib.enableRtn	= cacheArchEnable;	/* cacheEnable() */
        cacheLib.disableRtn	= cacheArchDisable;	/* cacheDisable() */
        cacheLib.lockRtn	= cacheArchLock;	/* cacheLock() */
        cacheLib.unlockRtn	= cacheArchUnlock;	/* cacheUnlock() */
        cacheLib.clearRtn	= cacheArchClear;	/* cacheClear() */
        cacheLib.dmaMallocRtn	= (FUNCPTR)cacheArchDmaMalloc;
        cacheLib.dmaFreeRtn	= (FUNCPTR)cacheArchDmaFree;
        cacheLib.dmaVirtToPhysRtn = NULL;
        cacheLib.dmaPhysToVirtRtn = NULL;
        cacheLib.textUpdateRtn	= NULL;

        cacheLib.flushRtn	= cacheArchFlush;	/* cacheFlush() */
        cacheLib.invalidateRtn	= cacheArchClear;	/* cacheClear() */
        cacheLib.pipeFlushRtn	= NULL;

	if ((sysProcessor == X86CPU_PENTIUMPRO) &&
	    (dataMode & CACHE_SNOOP_ENABLE))
	    {
	    /* fully coherent cache with MESI protocol */

            cacheLib.lockRtn	= NULL;			/* cacheLock() */
            cacheLib.unlockRtn	= NULL;			/* cacheUnlock() */
            cacheLib.clearRtn	= NULL;			/* cacheClear() */
            cacheLib.dmaMallocRtn = NULL;
            cacheLib.dmaFreeRtn	= NULL;
            cacheLib.flushRtn	= NULL;			/* cacheFlush() */
            cacheLib.invalidateRtn = NULL;		/* cacheClear() */
	    }

        if ((instMode & CACHE_WRITEALLOCATE)	|| 
	    (dataMode & CACHE_WRITEALLOCATE)	||
            (instMode & CACHE_NO_WRITEALLOCATE)	|| 
	    (dataMode & CACHE_NO_WRITEALLOCATE)	||
            (instMode & CACHE_SNOOP_ENABLE)	|| 
            (instMode & CACHE_SNOOP_DISABLE)	|| 
            (instMode & CACHE_BURST_ENABLE)	|| 
	    (dataMode & CACHE_BURST_ENABLE)	||
            (instMode & CACHE_BURST_DISABLE)	|| 
	    (dataMode & CACHE_BURST_DISABLE))
	    return (ERROR);

        cache486Reset ();			/* reset and disable a cache */
	}

    cacheDataMode		= dataMode;	/* save dataMode for enable */
    cacheDataEnabled		= FALSE;	/* d-cache is currently off */
    cacheMmuAvailable		= FALSE;	/* no mmu yet */

    return (OK);
    }

/*******************************************************************************
*
* cacheArchEnable - enable a cache
*
* This routine enables the 486 cache.
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchEnable
    (
    CACHE_TYPE	cache		/* cache to enable */
    )
    {

    cache486Enable ();

    if (cache == DATA_CACHE)
	{
	cacheDataEnabled = TRUE;
	cacheFuncsSet ();
	}

    return (OK);
    }

/*******************************************************************************
*
* cacheArchDisable - disable a cache
*
* This routine disables the 486 cache.
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchDisable
    (
    CACHE_TYPE	cache		/* cache to disable */
    )
    {

    cache486Disable ();

    if (cache == DATA_CACHE)
	{
	cacheDataEnabled = FALSE;		/* data cache is off */
	cacheFuncsSet ();			/* update data function ptrs */
	}

    return (OK);
    }

/*******************************************************************************
*
* cacheArchLock - lock entries in a cache
*
* This routine locks all entries in the 486 cache.
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchLock
    (
    CACHE_TYPE	cache, 		/* cache to lock */
    void *	address,	/* address to lock */
    size_t	bytes		/* bytes to lock (ENTIRE_CACHE) */
    )
    {

    cache486Lock ();
    return (OK);
    }

/*******************************************************************************
*
* cacheArchUnlock - unlock a cache
*
* This routine unlocks all entries in the 486 cache.
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchUnlock
    (
    CACHE_TYPE	cache, 		/* cache to unlock */
    void *	address,	/* address to unlock */
    size_t	bytes		/* bytes to unlock (ENTIRE_CACHE) */
    )
    {

    cache486Unlock ();
    return (OK);
    }

/*******************************************************************************
*
* cacheArchClear - clear all entries from a cache
*
* This routine clears all entries from the 486 cache.  
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchClear
    (
    CACHE_TYPE	cache, 		/* cache to clear */
    void *	address,	/* address to clear */
    size_t	bytes		/* bytes to clear */
    )
    {

    cache486Clear ();
    return (OK);
    }

/*******************************************************************************
*
* cacheArchFlush - flush all entries from a cache
*
* This routine flushs all entries from the 486 cache.  
* If the CPU is 386 or PENTIUNPRO with SNOOP_ENABLED data cache mode, it does
* nothing.
*
* RETURNS: OK.
*
* NOMANUAL
*/

STATUS cacheArchFlush
    (
    CACHE_TYPE	cache, 		/* cache to clear */
    void *	address,	/* address to clear */
    size_t	bytes		/* bytes to clear */
    )
    {

    /* do nothing if it is "386" or "P6 with snoop enabled" */

    if ((sysProcessor == X86CPU_386) ||
        ((sysProcessor == X86CPU_PENTIUMPRO) &&
	 (cacheDataMode & CACHE_SNOOP_ENABLE)))
        return (OK);

    cache486Flush ();
    return (OK);
    }

/*******************************************************************************
*
* cacheArchClearEntry - clear an entry from a cache
*
* This routine clears a specified entry from the 486 cache.
* If the CPU is 386 or PENTIUNPRO with SNOOP_ENABLED data cache mode, it does
* nothing.
*
* For I80X86 processors, this routine clears the cache.
*
* RETURNS: OK
*/

STATUS cacheArchClearEntry
    (
    CACHE_TYPE	cache,		/* cache to clear entry for */
    void *	address		/* entry to clear */
    )
    {

    /* do nothing if it is "386" or "P6 with snoop enabled" */

    if ((sysProcessor == X86CPU_386) ||
        ((sysProcessor == X86CPU_PENTIUMPRO) &&
	 (cacheDataMode & CACHE_SNOOP_ENABLE)))
        return (OK);

    cache486Clear ();
    return (OK);
    }

/*******************************************************************************
*
* cacheArchDmaMalloc - allocate a cache-safe buffer
*
* This routine attempts to return a pointer to a section of memory
* that will not experience cache coherency problems.  This routine
* is only called when MMU support is available 
* for cache control.
*
* INTERNAL
* We check if the cache is actually on before allocating the memory.  It
* is possible that the user wants Memory Management Unit (MMU)
* support but does not need caching.
*
* RETURNS: A pointer to a cache-safe buffer, or NULL.
*
* SEE ALSO: cacheArchDmaFree(), cacheDmaMalloc()
*
* NOMANUAL
*/

void *cacheArchDmaMalloc 
    (
    size_t      bytes			/* size of cache-safe buffer */
    )
    {
    void *pBuf;
    int	  pageSize;

    if ((pageSize = VM_PAGE_SIZE_GET ()) == ERROR)
	return (NULL);

    /* make sure bytes is a multiple of pageSize */

    bytes = bytes / pageSize * pageSize + pageSize;

    if ((_func_valloc == NULL) || 
	((pBuf = (void *)(* _func_valloc) (bytes)) == NULL))
	return (NULL);

    VM_STATE_SET (NULL, pBuf, bytes,
		  VM_STATE_MASK_CACHEABLE, VM_STATE_CACHEABLE_NOT);

    return (pBuf);
    }
	
/*******************************************************************************
*
* cacheArchDmaFree - free the buffer acquired by cacheArchDmaMalloc()
*
* This routine returns to the free memory pool a block of memory previously
* allocated with cacheArchDmaMalloc().  The buffer is marked cacheable.
*
* RETURNS: OK, or ERROR if cacheArchDmaMalloc() cannot be undone.
*
* SEE ALSO: cacheArchDmaMalloc(), cacheDmaFree()
*
* NOMANUAL
*/

STATUS cacheArchDmaFree
    (
    void *pBuf		/* ptr returned by cacheArchDmaMalloc() */
    )
    {
    BLOCK_HDR *	pHdr;			/* pointer to block header */
    STATUS	status = OK;		/* return value */

    if (vmLibInfo.vmLibInstalled)
	{
	pHdr = BLOCK_TO_HDR (pBuf);

	status = VM_STATE_SET (NULL,pBuf,(pHdr->nWords * 2) - sizeof(BLOCK_HDR),
			       VM_STATE_MASK_CACHEABLE, VM_STATE_CACHEABLE);
	}

    free (pBuf);			/* free buffer after modified */

    return (status);
    }