dsmlib.c

vxworks源码源码解读是学习vxworks的最佳途径

/* dsmLib.c - i80x86 disassembler */

/* Copyright 1984-1998 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01i,06may98,fle  added P5 and P6 related instructions and facilities
01h,14nov94,hdn  changed D->DISR, W->WFUL, S->SEXT, P->POP, A->AX, I->IMM.
01g,29may94,hdn  removed I80486.
01f,31aug93,hdn  changed a type of 1st parameter, from char to UCHAR.
01e,02aug93,hdn  fixed a case that has mod=0,rm=5,disp32 operand.
01d,01jun93,hdn  updated to 5.1
		  - changed functions to ansi style
		  - fixed #else and #endif
		  - changed VOID to void
		  - changed copyright notice
01c,18mar93,hdn  supported 486 instructions.
01b,05nov92,hdn  supported "16 bit operand","rep","repne","shift by 1".
		 fixed a bug that is about "empty index".
01a,23jun92,hdn  written. 
*/

/*
This library contains everything necessary to print i80x86 object code in
assembly language format. 

The programming interface is via dsmInst(), which prints a single disassembled
instruction, and dsmNbytes(), which reports the size of an instruction.

To disassemble from the shell, use l(), which calls this
library to do the actual work.  See dbgLib for details.

INCLUDE FILE: dsmLib.h

SEE ALSO: dbgLib
*/

#include "vxWorks.h"
#include "dsmLib.h"
#include "symLib.h"
#include "string.h"
#include "stdio.h"
#include "errnoLib.h"

/*
 * This table is ordered by the number of bits in an instruction's 
 * two word mask, beginning with the greatest number of bits in masks.  
 * This scheme is used for avoiding conflicts between instructions 
 * when matching bit patterns.  The instruction ops are arranged 
 * sequentially within each group of instructions for a particular 
 * mask so that uniqueness can be easily spotted.  
 */

/* globals */

LOCAL OP3MASK op3 [] =
    {
    /* additional 3 bits mask for OP3 instructions */
    {0x20, 0x38},			/* BT		16 + 3 bits */
    {0x38, 0x38},			/* BTC		16 + 3 bits */
    {0x30, 0x38},			/* BTR		16 + 3 bits */
    {0x28, 0x38},			/* BTS		16 + 3 bits */
    {0x10, 0x38},			/* LGDT		16 + 3 bits */
    {0x18, 0x38},			/* LIDT		16 + 3 bits */
    {0x10, 0x38},			/* LLDT		16 + 3 bits */
    {0x30, 0x38},			/* LMSW		16 + 3 bits */
    {0x08, 0x38},			/* LTR		16 + 3 bits */
    {0x00, 0x38},			/* SGDT		16 + 3 bits */
    {0x08, 0x38},			/* SIDT		16 + 3 bits */
    {0x00, 0x38},			/* SLDT		16 + 3 bits */
    {0x20, 0x38},			/* SMSW		16 + 3 bits */
    {0x08, 0x38},			/* STR		16 + 3 bits */
    {0x20, 0x38},			/* VERR		16 + 3 bits */
    {0x28, 0x38},			/* VERW		16 + 3 bits */
    {0xf0, 0xf8},			/* PSLL         14 + 5 bits */
    {0xe0, 0xf8},			/* PSRA         14 + 5 bits */
    {0xd0, 0xf8},			/* PSRL         14 + 5 bits */
    {0x00, 0x00},			/* CMOV         12 + 3 bits */
    {0x00, 0x38},			/* CSET		12 + 3 bits */
    {0, 0},				/* terminator               */
    };

LOCAL INST inst [] =
    {
    /* 16+3 bits mask */
    {"BT", itBtI,		OP3|MODRM|I8,		0x0f, 0xba, 0xff, 0xff},
    {"BTC", itBtcI,		OP3|MODRM|I8,		0x0f, 0xba, 0xff, 0xff},
    {"BTR", itBtrI,		OP3|MODRM|I8,		0x0f, 0xba, 0xff, 0xff},
    {"BTS", itBtsI,		OP3|MODRM|I8,		0x0f, 0xba, 0xff, 0xff},
    {"LGDT", itLgdt,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"LIDT", itLidt,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"LLDT", itLldt,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},
    {"LMSW", itLmsw,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"LTR", itLtr,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},
    {"SGDT", itSgdt,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"SIDT", itSidt,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"SLDT", itSldt,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},
    {"SMSW", itSmsw,		OP3|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"STR", itStr,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},
    {"VERR", itVerr,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},
    {"VERW", itVerw,		OP3|MODRM,		0x0f, 0x00, 0xff, 0xff},

    /* 16 bits mask */
    {"AAD", itAad,		OP2,			0xd5, 0x0a, 0xff, 0xff},
    {"AAM", itAam,		OP2,			0xd4, 0x0a, 0xff, 0xff},
    {"BSF", itBsf,		OP2|MODRM|REG,		0x0f, 0xbc, 0xff, 0xff},
    {"BSR", itBsr,		OP2|MODRM|REG,		0x0f, 0xbd, 0xff, 0xff},
    {"BT", itBtR,		OP2|MODRM|REG,		0x0f, 0xa3, 0xff, 0xff},
    {"BTC", itBtcR,		OP2|MODRM|REG,		0x0f, 0xbb, 0xff, 0xff},
    {"BTR", itBtrR,		OP2|MODRM|REG,		0x0f, 0xb3, 0xff, 0xff},
    {"BTS", itBtsR,		OP2|MODRM|REG,		0x0f, 0xab, 0xff, 0xff},
    {"CLTS", itClts,		OP2,			0x0f, 0x06, 0xff, 0xff},
    {"CMPXCHG8B", itCmpxchg8b,	OP2|MODRM,		0x0f, 0xc7, 0xff, 0xff},
    {"CPUID", itCpuid,		OP2,			0x0f, 0xa2, 0xff, 0xff},
    {"EMMS", itEmms,		OP2,			0x0f, 0x77, 0xff, 0xff},
    {"F2XM1", itF2xm1,		OP2,		ESC|0x01, 0xf0, 0xff, 0xff},
    {"FABS", itFabs,		OP2,		ESC|0x01, 0xe1, 0xff, 0xff},
    {"FCHS", itFchs,		OP2,		ESC|0x01, 0xe0, 0xff, 0xff},
    {"FCLEX", itFclex,		OP2,		ESC|0x03, 0xe2, 0xff, 0xff},
    {"FCOMPP", itFcompp,	OP2,		ESC|0x06, 0xd9, 0xff, 0xff},
    {"FCOS", itFcos,		OP2,		ESC|0x01, 0xff, 0xff, 0xff},
    {"FDECSTP", itFdecstp,	OP2,		ESC|0x01, 0xf6, 0xff, 0xff},
    {"FINCSTP", itFincstp,	OP2,		ESC|0x01, 0xf7, 0xff, 0xff},
    {"FINIT", itFinit,		OP2,		ESC|0x03, 0xe3, 0xff, 0xff},
    {"FLDZ", itFldZ,		OP2,		ESC|0x01, 0xee, 0xff, 0xff},
    {"FLD1", itFld1,		OP2,		ESC|0x01, 0xe8, 0xff, 0xff},
    {"FLDPI", itFldPI,		OP2,		ESC|0x01, 0xeb, 0xff, 0xff},
    {"FLDL2T", itFldL2T,	OP2,		ESC|0x01, 0xe9, 0xff, 0xff},
    {"FLDL2E", itFldL2E,	OP2,		ESC|0x01, 0xea, 0xff, 0xff},
    {"FLDLG2", itFldLG2,	OP2,		ESC|0x01, 0xec, 0xff, 0xff},
    {"FLDLN2", itFldLN2,	OP2,		ESC|0x01, 0xed, 0xff, 0xff},
    {"FNOP", itFnop,		OP2,		ESC|0x01, 0xd0, 0xff, 0xff},
    {"FPATAN", itFpatan,	OP2,		ESC|0x01, 0xf3, 0xff, 0xff},
    {"FPREM", itFprem,		OP2,		ESC|0x01, 0xf8, 0xff, 0xff},
    {"FPREM1", itFprem1,	OP2,		ESC|0x01, 0xf5, 0xff, 0xff},
    {"FPTAN", itFptan,		OP2,		ESC|0x01, 0xf2, 0xff, 0xff},
    {"FRNDINT", itFrndint,	OP2,		ESC|0x01, 0xfc, 0xff, 0xff},
    {"FSCALE", itFscale,	OP2,		ESC|0x01, 0xfd, 0xff, 0xff},
    {"FSIN", itFsin,		OP2,		ESC|0x01, 0xfe, 0xff, 0xff},
    {"FSINCOS", itFsincos,	OP2,		ESC|0x01, 0xfb, 0xff, 0xff},
    {"FSQRT", itFsqrt,		OP2,		ESC|0x01, 0xfa, 0xff, 0xff},
    {"FSTSW", itFstswA,		OP2|AX,		ESC|0x07, 0xe0, 0xff, 0xff},
    {"FTST", itFtst,		OP2,		ESC|0x01, 0xe4, 0xff, 0xff},
    {"FUCOMPP", itFucompp,	OP2,		ESC|0x02, 0xe9, 0xff, 0xff},
    {"FXAM", itFxam,		OP2,		ESC|0x01, 0xe5, 0xff, 0xff},
    {"FXTRACT", itFxtract,	OP2,		ESC|0x01, 0xf4, 0xff, 0xff},
    {"FYL2X", itFyl2x,		OP2,		ESC|0x01, 0xf1, 0xff, 0xff},
    {"FYL2XP1", itFyl2xp1,	OP2,		ESC|0x01, 0xf9, 0xff, 0xff},
    {"IMUL", itImulRwiRM,	OP2|MODRM|REG,		0x0f, 0xaf, 0xff, 0xff},
    {"INVD", itInvd,		OP2,			0x0f, 0x08, 0xff, 0xff},
    {"INVLPG", itInvlpg,	OP2|MODRM,		0x0f, 0x01, 0xff, 0xff},
    {"LAR", itLar,		OP2|MODRM|REG,		0x0f, 0x02, 0xff, 0xff},
    {"LFS", itLfs,		OP2|MODRM|REG,		0x0f, 0xb4, 0xff, 0xff},
    {"LGS", itLgs,		OP2|MODRM|REG,		0x0f, 0xb5, 0xff, 0xff},
    {"LSL", itLsl,		OP2|MODRM|REG,		0x0f, 0x03, 0xff, 0xff},
    {"LSS", itLss,		OP2|MODRM|REG,		0x0f, 0xb2, 0xff, 0xff},
    {"MOV", itMovC,		OP2|DISR|EEE|MODRM,	0x0f, 0x22, 0xff, 0xff},
    {"MOV", itMovC,		OP2|DISR|EEE|MODRM,	0x0f, 0x20, 0xff, 0xff},
    {"MOV", itMovD,		OP2|DISR|EEE|MODRM,	0x0f, 0x23, 0xff, 0xff},
    {"MOV", itMovD,		OP2|DISR|EEE|MODRM,	0x0f, 0x21, 0xff, 0xff},
    {"MOV", itMovT,		OP2|DISR|EEE|MODRM,	0x0f, 0x26, 0xff, 0xff},
    {"MOV", itMovT,		OP2|DISR|EEE|MODRM,	0x0f, 0x24, 0xff, 0xff},
    {"MOVD", itMovd,		OP2|MMXREG|MODRM,	0x0f, 0x7e, 0xff, 0xff},
    {"MOVD", itMovd,		OP2|MMXREG|MODRM,	0x0f, 0x6e, 0xff, 0xff},
    {"MOVQ", itMovq,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0x6f, 0xff, 0xff},
    {"MOVQ", itMovq,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0x7f, 0xff, 0xff},
    {"PACKSSDW", itPackssdw,	OP2|MMXREG|MMXRM|MODRM,	0x0f, 0x6b, 0xff, 0xff},
    {"PACKSSWB", itPacksswb,	OP2|MMXREG|MMXRM|MODRM,	0x0f, 0x63, 0xff, 0xff},
    {"PACKUSWB", itPackuswb,	OP2|MMXREG|MMXRM|MODRM,	0x0f, 0x67, 0xff, 0xff},
    {"PAND", itPand,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xdb, 0xff, 0xff},
    {"PANDN", itPandn,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xdf, 0xff, 0xff},
    {"PMADD", itPmadd,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xf5, 0xff, 0xff},
    {"PMULH", itPmulh,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xe5, 0xff, 0xff},
    {"PMULL", itPmull,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xd5, 0xff, 0xff},
    {"POR", itPor,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xeb, 0xff, 0xff},
    {"PXOR", itPxor,		OP2|MMXREG|MMXRM|MODRM,	0x0f, 0xef, 0xff, 0xff},
    {"RDTSC", itRdtsc,		OP2,			0x0f, 0x31, 0xff, 0xff},
    {"RDMSR", itRdmsr,		OP2,			0x0f, 0x32, 0xff, 0xff},
    {"RDPMC", itRdpmc,		OP2,			0x0f, 0x33, 0xff, 0xff},
    {"RSM", itRsm,		OP2,			0x0f, 0xaa, 0xff, 0xff},
    {"SHLD", itShldRMbyI,	OP2|MODRM|REG|I8,	0x0f, 0xa4, 0xff, 0xff},
    {"SHLD", itShldRMbyCL,	OP2|MODRM|REG|CL,	0x0f, 0xa5, 0xff, 0xff},
    {"SHRD", itShrdRMbyI,	OP2|MODRM|REG|I8,	0x0f, 0xac, 0xff, 0xff},
    {"SHRD", itShrdRMbyCL,	OP2|MODRM|REG|CL,	0x0f, 0xad, 0xff, 0xff},
    {"UD2", itUd2,		OP2,			0x0f, 0x0b, 0xff, 0xff},
    {"WBINVD", itWbinvd,	OP2,			0x0f, 0x09, 0xff, 0xff},
    {"WRMSR", itWrmsr,		OP2,			0x0f, 0x30, 0xff, 0xff},

    /* 15 bits mask */
    {"CMPXCHG", itCmpxchg,	OP2|WFUL|MODRM|REG,	0x0f, 0xb0, 0xff, 0xfe},
    {"MOVSX", itMovsx,		OP2|WFUL|MODRM|REG,	0x0f, 0xbe, 0xff, 0xfe},
    {"MOVZX", itMovzx,		OP2|WFUL|MODRM|REG,	0x0f, 0xb6, 0xff, 0xfe},
    {"REP INS", itRins,		OP2|WFUL,		0xf3, 0x6c, 0xff, 0xfe},
    {"REP LODS", itRlods,	OP2|WFUL,		0xf3, 0xac, 0xff, 0xfe},
    {"REP MOVS", itRmovs,	OP2|WFUL,		0xf3, 0xa4, 0xff, 0xfe},
    {"REP OUTS", itRouts,	OP2|WFUL,		0xf3, 0x6e, 0xff, 0xfe},
    {"REP STOS", itRstos,	OP2|WFUL,		0xf3, 0xaa, 0xff, 0xfe},
    {"REPE CMPS", itRcmps,	OP2|WFUL,		0xf3, 0xa6, 0xff, 0xfe},
    {"REPE SCAS", itRscas,	OP2|WFUL,		0xf3, 0xae, 0xff, 0xfe},
    {"REPNE CMPS", itRNcmps,	OP2|WFUL,		0xf2, 0xa6, 0xff, 0xfe},
    {"REPNE SCAS", itRNscas,	OP2|WFUL,		0xf2, 0xae, 0xff, 0xfe},
    {"XADD", itXadd,		OP2|WFUL|MODRM|REG,	0x0f, 0xc0, 0xff, 0xfe},

    /* 14 + 5 bits mask */
    {"PSLL", itPsll,		OP3|GG|MODRM|MMXRM|I8,	0x0f, 0x70, 0xff, 0xfc},
    {"PSRA", itPsra,		OP3|GG|MODRM|MMXRM|I8,	0x0f, 0x70, 0xff, 0xfc},
    {"PSRL", itPsrl,		OP3|GG|MODRM|MMXRM|I8,	0x0f, 0x70, 0xff, 0xfc},

    /* 14 bits mask */
    {"PADD", itPadd,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xfc,
								0xff, 0xfc},
    {"PADDS", itPadds,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xec,
								0xff, 0xfc},
    {"PADDUS", itPaddus,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xdc,
								0xff, 0xfc},
    {"PCMPEQ", itPcmpeq,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0x74,
								0xff, 0xfc},
    {"PCMPGT", itPcmpgt,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0x64,
								0xff, 0xfc},
    {"PSLL", itPsll,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xf0,
								0xff, 0xfc},
    {"PSRA", itPsra,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xe0,
								0xff, 0xfc},
    {"PSRL", itPsrl,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xd0,
								0xff, 0xfc},
    {"PSUB", itPsub,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xf8,
								0xff, 0xfc},
    {"PSUBS", itPsubs,		OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xe8,
								0xff, 0xfc},
    {"PSUBUS", itPsubus,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0xd8,
								0xff, 0xfc},
    {"PUNPCKH", itPunpckh,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0x68,
								0xff, 0xfc},
    {"PUNPCKL", itPunpckl,	OP2|GG|MMXREG|MMXRM|MODRM,	0x0f, 0x60,
								0xff, 0xfc},

    /* 13 bits mask */
    {"BSWAP", itBswap,		OP1|MODRM,		0x0f, 0xc8, 0xff, 0xf8},
    {"FCMOVB", itFcmovb,	OP2|ST,		ESC|0x02, 0xc0, 0xff, 0xf8},
    {"FCMOVBE", itFcmovbe,	OP2|ST,		ESC|0x02, 0xd0, 0xff, 0xf8},
    {"FCMOVE",	itFcmove,	OP2|ST,		ESC|0x02, 0xc8, 0xff, 0xf8},
    {"FCMOVU", itFcmovu,	OP2|ST,		ESC|0x02, 0xd8, 0xff, 0xf8},
    {"FCMOVNB", itFcmovnb,	OP2|ST,		ESC|0x03, 0xc0, 0xff, 0xf8},
    {"FCMOVNBE", itFcmovnbe,	OP2|ST,		ESC|0x03, 0xd0, 0xff, 0xf8},
    {"FCMOVNE", itFcmovne,	OP2|ST,		ESC|0x03, 0xc8, 0xff, 0xf8},
    {"FCMOVNU", itFcmovnu,	OP2|ST,		ESC|0x03, 0xd8, 0xff, 0xf8},
    {"FCOM", itFcomST,		OP2|ST,		ESC|0x00, 0xd0, 0xff, 0xf8},
    {"FCOMI", itFcomi,		OP2|ST,		ESC|0x03, 0xf0, 0xff, 0xf8},
    {"FCOMP", itFcompST,	OP2|ST,		ESC|0x00, 0xd8, 0xff, 0xf8},
    {"FFREE", itFfree,		OP2|ST,		ESC|0x05, 0xc0, 0xff, 0xf8},
    {"FLD", itFldST,		OP2|ST,		ESC|0x01, 0xc0, 0xff, 0xf8},
    {"FST", itFstST,		OP2|ST,		ESC|0x05, 0xd0, 0xff, 0xf8},
    {"FSTP", itFstpST,		OP2|ST,		ESC|0x05, 0xd8, 0xff, 0xf8},
    {"FUCOM", itFucom,		OP2|ST,		ESC|0x05, 0xe0, 0xff, 0xf8},
    {"FUCOMP", itFucomp,	OP2|ST,		ESC|0x05, 0xe8, 0xff, 0xf8},
    {"FXCH", itFxch,		OP2|ST,		ESC|0x01, 0xc8, 0xff, 0xf8},
    {"POP", itPopS,		OP2|REG,		0x0f, 0x81, 0xff, 0xc7},
    {"PUSH", itPushS,		OP1|SREG3,		0x0f, 0x80, 0xff, 0xc7},

    /* 12 + 3 bits mask */
    {"CMOV", itCmovcc,		OP3|TTTN|MODRM|REG,	0x0f, 0x40, 0xff, 0xf0},
    {"CSET", itCset,		OP3|TTTN|MODRM,		0x0f, 0x90, 0xff, 0xf0},

    /* 12 bits mask */
    {"CJMPF", itCjmp,		OP2|TTTN|DIS,		0x0f, 0x80, 0xff, 0xf0},

    /* 11 bits mask */
    {"CALL", itCallRM,		OP1|MODRM,		0xff, 0x10, 0xff, 0x38},
    {"CALL", itCallSegRM,	OP1|MODRM,		0xff, 0x18, 0xff, 0x38},
    {"FADD", itFaddST,		OP2|POP|FD|ST,	ESC|0x00, 0xc0, 0xf9, 0xf8},
    {"FLDbcd", itFldBCDM,	OP1|MODRM,	ESC|0x07, 0x20, 0xff, 0x38},
    {"FLDCW", itFldcw,		OP1|MODRM,	ESC|0x01, 0x28, 0xff, 0x38},
    {"FLDENV", itFldenv,	OP1|MODRM,	ESC|0x01, 0x20, 0xff, 0x38},
    {"FLDext", itFldERM,	OP1|MODRM,	ESC|0x03, 0x28, 0xff, 0x38},
    {"FLDint", itFldLIM,	OP1|MODRM,	ESC|0x07, 0x28, 0xff, 0x38},
    {"FMUL", itFmulST,		OP2|POP|FD|ST,	ESC|0x00, 0xc8, 0xf9, 0xf8},
    {"FRSTOR", itFrstor,	OP1|MODRM,	ESC|0x05, 0x20, 0xff, 0x38},
    {"FSAVE", itFsave,		OP1|MODRM,	ESC|0x05, 0x30, 0xff, 0x38},
    {"FSTCW", itFstcw,		OP1|MODRM,	ESC|0x01, 0x38, 0xff, 0x38},
    {"FSTENV", itFstenv,	OP1|MODRM,	ESC|0x01, 0x30, 0xff, 0x38},
    {"FSTPbcd", itFstpBCDM,	OP1|MODRM,	ESC|0x07, 0x30, 0xff, 0x38},
    {"FSTPext", itFstpERM,	OP1|MODRM,	ESC|0x03, 0x38, 0xff, 0x38},
    {"FSTPint", itFstpLIM,	OP1|MODRM,	ESC|0x07, 0x38, 0xff, 0x38},
    {"FSTSW", itFstsw,		OP1|MODRM,	ESC|0x05, 0x38, 0xff, 0x38},
    {"IMUL", itImulAwiRM,	OP1|WFUL|MODRM|AX,	0xf6, 0x28, 0xff, 0x38},
    {"JMP", itJmpRM,		OP1|MODRM,		0xff, 0x20, 0xff, 0x38},
    {"JMP", itJmpSegRM,		OP1|MODRM,		0xff, 0x28, 0xff, 0x38},
    {"POP", itPopRM,		OP1|MODRM,		0x8f, 0x00, 0xff, 0x38},
    {"PUSH", itPushRM,		OP1|MODRM,		0xff, 0x30, 0xff, 0x38},

    /* 10 bits mask */
    {"DEC", itDecRM,		OP1|WFUL|MODRM,		0xfe, 0x08, 0xfe, 0x38},
    {"DIV", itDiv,		OP1|WFUL|MODRM|AX,	0xf6, 0x30, 0xfe, 0x38},
    {"FDIV", itFdivST,		OP2|POP|FD|ST,	ESC|0x00, 0xf0, 0xf9, 0xf0},
    {"FSUB", itFsubST,		OP2|POP|FD|ST,	ESC|0x00, 0xe0, 0xf9, 0xf0},
    {"IDIV", itIdiv,		OP1|WFUL|MODRM|AX,	0xf6, 0x38, 0xfe, 0x38},
    {"INC", itIncRM,		OP1|WFUL|MODRM,		0xfe, 0x00, 0xfe, 0x38},
    {"MOV", itMovItoRM,		OP1|WFUL|MODRM|IMM,	0xc6, 0x00, 0xfe, 0x38},
    {"MUL", itMulAwiRM,		OP1|WFUL|MODRM|AX,	0xf6, 0x20, 0xfe, 0x38},
    {"NEG", itNeg,		OP1|WFUL|MODRM,		0xf6, 0x18, 0xfe, 0x38},
    {"NOT", itNot,		OP1|WFUL|MODRM,		0xf6, 0x10, 0xfe, 0x38},
    {"TEST", itTestIanRM,	OP1|WFUL|MODRM|IMM,	0xf6, 0x00, 0xfe, 0x38},

    /* 9 bits mask */
    {"ADD", itAddItoRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x00, 0xfc, 0x38},
    {"ADC", itAdcItoRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x10, 0xfc, 0x38},
    {"AND", itAndItoRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x20, 0xfc, 0x38},
    {"CMP", itCmpIwiRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x38, 0xfc, 0x38},
    {"FADD", itFaddIRM,		OP1|MF|MODRM,	ESC|0x00, 0x00, 0xf9, 0x38},
    {"FCOM", itFcomIRM,		OP1|MF|MODRM,	ESC|0x00, 0x10, 0xf9, 0x38},
    {"FCOMP", itFcompIRM,	OP1|MF|MODRM,	ESC|0x00, 0x18, 0xf9, 0x38},
    {"FLD", itFldIRM,		OP1|MF|MODRM,	ESC|0x01, 0x00, 0xf9, 0x38},
    {"FMUL", itFmulIRM,		OP1|MF|MODRM,	ESC|0x00, 0x08, 0xf9, 0x38},
    {"FST", itFstIRM,		OP1|MF|MODRM,	ESC|0x01, 0x10, 0xf9, 0x38},
    {"FSTP", itFstpIRM,		OP1|MF|MODRM,	ESC|0x01, 0x18, 0xf9, 0x38},
    {"OR", itOrItoRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x08, 0xfc, 0x38},
    {"SBB", itSbbIfrRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x18, 0xfc, 0x38},
    {"SUB", itSubIfrRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x28, 0xfc, 0x38},
    {"XOR", itXorItoRM,		OP1|SEXT|WFUL|MODRM|IMM,0x80, 0x30, 0xfc, 0x38},

    /* 8 bits mask */
    {"AAA", itAaa,		OP1,			0x37, 0x00, 0xff, 0x00},
    {"AAS", itAas,		OP1,			0x3f, 0x00, 0xff, 0x00},
    {"ARPL", itArpl,		OP1|MODRM|REG,		0x63, 0x00, 0xff, 0x00},
    {"ASIZE", itAsize,		OP1,			0x67, 0x00, 0xff, 0x00},
    {"BOUND", itBound,		OP1|MODRM|REG,		0x62, 0x00, 0xff, 0x00},
    {"CALL", itCall,		OP1|DIS,		0xe8, 0x00, 0xff, 0x00},
    {"CALL", itCallSeg,		OP1|OFFSEL,		0x9a, 0x00, 0xff, 0x00},
    {"CBW", itCbw,		OP1,			0x98, 0x00, 0xff, 0x00},
    {"CLC", itClc,		OP1,			0xf8, 0x00, 0xff, 0x00},
    {"CLD", itCld,		OP1,			0xfc, 0x00, 0xff, 0x00},
    {"CLI", itCli,		OP1,			0xfa, 0x00, 0xff, 0x00},
    {"CMC", itCmc,		OP1,			0xf5, 0x00, 0xff, 0x00},
    {"CS", itCs,		OP1,			0x2e, 0x00, 0xff, 0x00},
    {"CWD", itCwd,		OP1,			0x99, 0x00, 0xff, 0x00},
    {"DAA", itDaa,		OP1,			0x27, 0x00, 0xff, 0x00},
    {"DAS", itDas,		OP1,			0x2f, 0x00, 0xff, 0x00},
    {"DS", itDs,		OP1,			0x3e, 0x00, 0xff, 0x00},
    {"ENTER", itEnter,		OP1|D16L8,		0xc8, 0x00, 0xff, 0x00},
    {"ES", itEs,		OP1,			0x26, 0x00, 0xff, 0x00},
    {"FDIV", itFdivIRM,		OP1|MF|MODRM,	ESC|0x00, 0x30, 0xf9, 0x30},
    {"FS", itFs,		OP1,			0x64, 0x00, 0xff, 0x00},
    {"FSUB", itFsubIRM,		OP1|MF|MODRM,	ESC|0x00, 0x20, 0xf9, 0x30},
    {"GS", itGs,		OP1,			0x65, 0x00, 0xff, 0x00},
    {"HLT", itHlt,		OP1,			0xf4, 0x00, 0xff, 0x00},
    {"INT", itInt,		OP1|TYPE,		0xcd, 0x00, 0xff, 0x00},
    {"INT", itInt3,		OP1,			0xcc, 0x00, 0xff, 0x00},
    {"INTO", itInto,		OP1,			0xce, 0x00, 0xff, 0x00},
    {"IRET", itIret,		OP1,			0xcf, 0x00, 0xff, 0x00},
    {"JECXZ", itJcxz,		OP1|D8,			0xe3, 0x00, 0xff, 0x00},
    {"JMP", itJmpS,		OP1|D8,			0xeb, 0x00, 0xff, 0x00},
    {"JMP", itJmpD,		OP1|DIS,		0xe9, 0x00, 0xff, 0x00},
    {"JMP", itJmpSeg,		OP1|OFFSEL,		0xea, 0x00, 0xff, 0x00},
    {"LAHF", itLahf,		OP1,			0x9f, 0x00, 0xff, 0x00},
    {"LDS", itLds,		OP1|MODRM|REG,		0xc5, 0x00, 0xff, 0x00},
    {"LEA", itLea,		OP1|MODRM|REG,		0x8d, 0x00, 0xff, 0x00},
    {"LEAVE", itLeave,		OP1,			0xc9, 0x00, 0xff, 0x00},
    {"LES", itLes,		OP1|MODRM|REG,		0xc4, 0x00, 0xff, 0x00},
    {"LOCK", itLock,		OP1,			0xf0, 0x00, 0xff, 0x00},
    {"LOOP", itLoop,		OP1|D8,			0xe2, 0x00, 0xff, 0x00},
    {"LOOPZ", itLoopz,		OP1|D8,			0xe1, 0x00, 0xff, 0x00},
    {"LOOPNZ", itLoopnz,	OP1|D8,			0xe0, 0x00, 0xff, 0x00},
    {"NOP", itNop,		OP1,			0x90, 0x00, 0xff, 0x00},
    {"OSIZE", itOsize,		OP1,			0x66, 0x00, 0xff, 0x00},
    {"POPA", itPopa,		OP1,			0x61, 0x00, 0xff, 0x00},
    {"POPF", itPopf,		OP1,			0x9d, 0x00, 0xff, 0x00},
    {"PUSHA", itPusha,		OP1,			0x60, 0x00, 0xff, 0x00},
    {"PUSHF", itPushf,		OP1,			0x9c, 0x00, 0xff, 0x00},
    {"REP", itRep,		OP1,			0xf3, 0x00, 0xff, 0x00},
    {"REPNE", itRepNe,		OP1,			0xf2, 0x00, 0xff, 0x00},
    {"RET", itRet,		OP1,			0xc3, 0x00, 0xff, 0x00},
    {"RET", itRetI,		OP1|D16,		0xc2, 0x00, 0xff, 0x00},
    {"RET", itRetSeg,		OP1,			0xcb, 0x00, 0xff, 0x00},
    {"RET", itRetSegI,		OP1|D16,		0xca, 0x00, 0xff, 0x00},
    {"SAHF", itSahf,		OP1,			0x9e, 0x00, 0xff, 0x00},
    {"SS", itSs,		OP1,			0x36, 0x00, 0xff, 0x00},
    {"STC", itStc,		OP1,			0xf9, 0x00, 0xff, 0x00},
    {"STD", itStd,		OP1,			0xfd, 0x00, 0xff, 0x00},
    {"STI", itSti,		OP1,			0xfb, 0x00, 0xff, 0x00},
    {"WAIT", itWait,		OP1,			0x9b, 0x00, 0xff, 0x00},
    {"XLAT", itXlat,		OP1|WFUL,		0xd7, 0x00, 0xff, 0x00},

    /* 7 bits mask */
    {"ADC", itAdcItoA,		SF|WFUL|IMM|AX,		0x14, 0x00, 0xfe, 0x00},
    {"ADD", itAddItoA,		SF|WFUL|IMM|AX,		0x04, 0x00, 0xfe, 0x00},
    {"AND", itAndItoA,		SF|WFUL|IMM|AX,		0x24, 0x00, 0xfe, 0x00},
    {"CMP", itCmpIwiA,		SF|WFUL|IMM|AX,		0x3c, 0x00, 0xfe, 0x00},
    {"CMPS", itCmps,		OP1|WFUL,		0xa6, 0x00, 0xfe, 0x00},
    {"IMUL", itImulRMwiI,	OP1|SEXT|MODRM|REG|IMM,	0x69, 0x00, 0xfd, 0x00},
    {"IN", itInF,		OP1|WFUL|PORT|AX,	0xe4, 0x00, 0xfe, 0x00},
    {"IN", itInV,		OP1|WFUL|AX,		0xec, 0x00, 0xfe, 0x00},
    {"INS", itIns,		OP1|WFUL,		0x6c, 0x00, 0xfe, 0x00},
    {"LODS", itLods,		OP1|WFUL,		0xac, 0x00, 0xfe, 0x00},
    {"MOV", itMovRMtoS,		OP1|DISR|MODRM|SREG3,	0x8c, 0x00, 0xfd, 0x00},
    {"MOVS", itMovs,		OP1|WFUL,		0xa4, 0x00, 0xfe, 0x00},
    {"OR", itOrItoA,		SF|WFUL|IMM|AX,		0x0c, 0x00, 0xfe, 0x00},
    {"OUT", itOutF,		OP1|WFUL|PORT|AX,	0xe6, 0x00, 0xfe, 0x00},
    {"OUT", itOutV,		OP1|WFUL|AX,		0xee, 0x00, 0xfe, 0x00},
    {"OUTS", itOuts,		OP1|WFUL,		0x6e, 0x00, 0xfe, 0x00},
    {"PUSH", itPushI,		OP1|SEXT|IMM,		0x68, 0x00, 0xfd, 0x00},