fp.vhd

来自「ProtelDXp 实现计算器功能」· VHDL 代码 · 共 29 行

-----------------------------       分    频    模     块      --------------------------------------  

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fp is
       Port ( clk     : in  std_logic;    -- CLK为时钟输入
              sec1 : out  std_logic);   --分频后的输出信号SEC1
end fp ;
architecture fpexc of fp is
   begin
   process(clk)
   variable c : integer range 0 to 200000;
         begin
         if  rising_edge(clk) then
               if c<200000 then c:=c+1;
               else c:=1;
               end if;
         end if;
         if c>190000 then sec1<='1';       --占空比为50％      
         else sec1<='0';
         end if;
   end process;
end fpexc;