reg4.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 682 行 · 第 1/3 页
RPT
682 行
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 4/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/0
Total: 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 16/0
Device-Specific Information: e:\cal\reg4.rpt
reg4
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - -- INPUT G ^ 0 0 0 0 CLR
79 - - - -- INPUT G ^ 0 0 0 0 INCLK
182 - - - -- INPUT ^ 0 0 0 1 OUTCODE0
80 - - - -- INPUT ^ 0 0 0 1 OUTCODE1
184 - - - -- INPUT ^ 0 0 0 1 OUTCODE2
183 - - - -- INPUT ^ 0 0 0 1 OUTCODE3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cal\reg4.rpt
reg4
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
133 - - D -- OUTPUT 0 1 0 0 AIN0
144 - - B -- OUTPUT 0 1 0 0 AIN1
116 - - I -- OUTPUT 0 1 0 0 AIN2
111 - - L -- OUTPUT 0 1 0 0 AIN3
135 - - D -- OUTPUT 0 1 0 0 BIN0
11 - - B -- OUTPUT 0 1 0 0 BIN1
37 - - I -- OUTPUT 0 1 0 0 BIN2
45 - - L -- OUTPUT 0 1 0 0 BIN3
134 - - D -- OUTPUT 0 1 0 0 CIN0
70 - - - 31 OUTPUT 0 1 0 0 CIN1
54 - - - 51 OUTPUT 0 1 0 0 CIN2
47 - - L -- OUTPUT 0 1 0 0 CIN3
16 - - D -- OUTPUT 0 1 0 0 DIN0
13 - - B -- OUTPUT 0 1 0 0 DIN1
207 - - - 51 OUTPUT 0 1 0 0 DIN2
67 - - - 33 OUTPUT 0 1 0 0 DIN3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\reg4.rpt
reg4
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - D 07 DFFE + 1 0 1 1 |reg1:1|Q0 (|reg1:1|:1)
- 3 - B 32 DFFE + 1 0 1 1 |reg1:1|Q1 (|reg1:1|:3)
- 5 - I 51 DFFE + 1 0 1 1 |reg1:1|Q2 (|reg1:1|:4)
- 5 - L 33 DFFE + 1 0 1 1 |reg1:1|Q3 (|reg1:1|:5)
- 1 - D 07 DFFE + 0 1 1 1 |reg1:2|Q0 (|reg1:2|:1)
- 1 - B 32 DFFE + 0 1 1 1 |reg1:2|Q1 (|reg1:2|:3)
- 2 - I 51 DFFE + 0 1 1 1 |reg1:2|Q2 (|reg1:2|:4)
- 3 - L 33 DFFE + 0 1 1 1 |reg1:2|Q3 (|reg1:2|:5)
- 5 - D 07 DFFE + 0 1 1 1 |reg1:3|Q0 (|reg1:3|:1)
- 6 - B 32 DFFE + 0 1 1 1 |reg1:3|Q1 (|reg1:3|:3)
- 1 - I 51 DFFE + 0 1 1 1 |reg1:3|Q2 (|reg1:3|:4)
- 8 - L 33 DFFE + 0 1 1 1 |reg1:3|Q3 (|reg1:3|:5)
- 2 - D 07 DFFE + 0 1 1 0 |reg1:4|Q0 (|reg1:4|:1)
- 8 - B 32 DFFE + 0 1 1 0 |reg1:4|Q1 (|reg1:4|:3)
- 3 - I 51 DFFE + 0 1 1 0 |reg1:4|Q2 (|reg1:4|:4)
- 1 - L 33 DFFE + 0 1 1 0 |reg1:4|Q3 (|reg1:4|:5)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\reg4.rpt
reg4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/208( 0%) 3/104( 2%) 0/104( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 2/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 1/208( 0%) 0/104( 0%) 2/104( 1%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\reg4.rpt
reg4
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 INCLK
Device-Specific Information: e:\cal\reg4.rpt
reg4
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 16 CLR
Device-Specific Information: e:\cal\reg4.rpt
reg4
** EQUATIONS **
CLR : INPUT;
INCLK : INPUT;
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