btobcd.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 970 行 · 第 1/5 页
RPT
970 行
7 - - A -- OUTPUT 0 1 0 0 BCD32
28 - - G -- OUTPUT 0 1 0 0 BCD33
139 - - C -- OUTPUT 0 1 0 0 BCD40
140 - - C -- OUTPUT 0 1 0 0 BCD41
136 - - C -- OUTPUT 0 1 0 0 BCD42
14 - - C -- OUTPUT 0 1 0 0 BCD43
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\btobcd.rpt
btobcd
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - C 02 AND2 s ! 0 0 0 1 CINA13~1
- 7 - L 14 OR2 4 0 0 2 |LPM_ADD_SUB:6580|addcore:adder|:95
- 4 - L 14 OR2 4 0 0 4 |LPM_ADD_SUB:6580|addcore:adder|:133
- 5 - L 14 OR2 4 0 0 4 |LPM_ADD_SUB:6601|addcore:adder|:95
- 6 - L 14 OR2 4 0 0 4 |LPM_ADD_SUB:6601|addcore:adder|:140
- 8 - L 02 OR2 3 0 0 3 |LPM_ADD_SUB:6601|addcore:adder|:151
- 8 - L 14 OR2 1 3 0 2 |LPM_ADD_SUB:6623|addcore:adder|:103
- 1 - L 14 OR2 0 4 0 1 |LPM_ADD_SUB:6623|addcore:adder|:107
- 2 - L 14 OR2 1 3 0 4 |LPM_ADD_SUB:6623|addcore:adder|:149
- 3 - L 14 OR2 0 4 0 3 |LPM_ADD_SUB:6623|addcore:adder|:150
- 4 - L 05 OR2 1 3 0 2 |LPM_ADD_SUB:6646|addcore:adder|:159
- 7 - L 02 OR2 2 2 0 3 |LPM_ADD_SUB:6670|addcore:adder|pcarry2
- 2 - L 05 OR2 1 3 0 2 |LPM_ADD_SUB:6670|addcore:adder|:115
- 1 - L 05 OR2 1 2 0 2 |LPM_ADD_SUB:6670|addcore:adder|:165
- 5 - L 05 OR2 1 3 0 4 |LPM_ADD_SUB:6670|addcore:adder|:166
- 6 - L 02 OR2 1 1 0 8 |LPM_ADD_SUB:6670|addcore:adder|:178
- 5 - L 02 OR2 2 2 0 4 |LPM_ADD_SUB:6670|addcore:adder|:179
- 8 - L 05 AND2 1 3 0 4 |LPM_ADD_SUB:6695|addcore:adder|:115
- 3 - L 05 OR2 1 3 0 4 |LPM_ADD_SUB:6695|addcore:adder|:173
- 4 - L 16 OR2 0 4 0 3 |LPM_ADD_SUB:6695|addcore:adder|:175
- 7 - L 16 OR2 0 4 0 2 |LPM_ADD_SUB:6695|addcore:adder|:176
- 5 - L 04 OR2 2 2 0 4 |LPM_ADD_SUB:6721|addcore:adder|:113
- 5 - L 16 OR2 0 4 0 3 |LPM_ADD_SUB:6721|addcore:adder|:123
- 7 - L 05 OR2 0 2 0 4 |LPM_ADD_SUB:6721|addcore:adder|:181
- 6 - L 05 OR2 0 4 0 3 |LPM_ADD_SUB:6721|addcore:adder|:182
- 8 - L 04 OR2 2 2 0 2 |LPM_ADD_SUB:6721|addcore:adder|:197
- 6 - L 16 OR2 1 3 0 3 |LPM_ADD_SUB:6748|addcore:adder|:127
- 6 - L 25 OR2 1 2 0 3 |LPM_ADD_SUB:6748|addcore:adder|:190
- 3 - L 16 OR2 0 3 0 3 |LPM_ADD_SUB:6748|addcore:adder|:191
- 1 - L 16 OR2 0 4 0 3 |LPM_ADD_SUB:6748|addcore:adder|:192
- 6 - L 04 OR2 2 2 0 3 |LPM_ADD_SUB:6776|addcore:adder|pcarry2
- 8 - L 25 OR2 1 2 0 3 |LPM_ADD_SUB:6776|addcore:adder|:127
- 1 - L 25 AND2 0 3 0 3 |LPM_ADD_SUB:6776|addcore:adder|:135
- 4 - L 25 OR2 1 2 0 4 |LPM_ADD_SUB:6776|addcore:adder|:197
- 3 - L 25 OR2 1 3 0 2 |LPM_ADD_SUB:6776|addcore:adder|:198
- 6 - L 06 OR2 0 2 0 1 |LPM_ADD_SUB:6776|addcore:adder|:200
- 4 - L 04 OR2 2 2 0 5 |LPM_ADD_SUB:6776|addcore:adder|:215
- 2 - L 04 OR2 3 1 0 5 |LPM_ADD_SUB:6805|addcore:adder|:121
- 7 - L 25 AND2 0 4 0 2 |LPM_ADD_SUB:6805|addcore:adder|:135
- 2 - L 25 OR2 0 4 0 2 |LPM_ADD_SUB:6805|addcore:adder|:139
- 8 - L 11 OR2 0 4 0 3 |LPM_ADD_SUB:6805|addcore:adder|:206
- 5 - L 25 OR2 0 4 0 2 |LPM_ADD_SUB:6805|addcore:adder|:207
- 1 - L 02 OR2 3 1 0 8 |LPM_ADD_SUB:6805|addcore:adder|:223
- 7 - L 04 OR2 1 3 0 3 |LPM_ADD_SUB:6835|addcore:adder|:135
- 6 - L 11 AND2 0 3 0 2 |LPM_ADD_SUB:6835|addcore:adder|:143
- 1 - L 04 OR2 1 3 0 7 |LPM_ADD_SUB:6835|addcore:adder|:213
- 8 - L 16 OR2 s 0 4 0 1 |LPM_ADD_SUB:6835|addcore:adder|~217~1
- 5 - L 06 OR2 s 0 4 0 1 |LPM_ADD_SUB:6835|addcore:adder|~217~2
- 2 - L 16 OR2 0 4 0 1 |LPM_ADD_SUB:6835|addcore:adder|:217
- 3 - L 04 OR2 1 2 0 10 |LPM_ADD_SUB:6835|addcore:adder|:233
- 4 - G 13 OR2 4 0 0 2 |LPM_ADD_SUB:6905|addcore:adder|:124
- 5 - G 13 OR2 3 0 0 2 |LPM_ADD_SUB:6905|addcore:adder|:125
- 3 - G 13 OR2 4 0 0 3 |LPM_ADD_SUB:6905|addcore:adder|:133
- 1 - G 18 OR2 1 3 0 2 |LPM_ADD_SUB:6925|addcore:adder|pcarry2
- 4 - G 17 OR2 3 0 0 3 |LPM_ADD_SUB:6925|addcore:adder|:80
- 7 - G 17 OR2 0 2 0 4 |LPM_ADD_SUB:6925|addcore:adder|:131
- 4 - G 07 OR2 0 2 0 3 |LPM_ADD_SUB:6925|addcore:adder|:133
- 5 - G 07 WIRE s 0 0 0 1 |LPM_ADD_SUB:6925|addcore:adder|~134~1
- 6 - G 07 AND2 s 0 0 0 1 |LPM_ADD_SUB:6925|addcore:adder|~134~2
- 7 - G 07 OR2 0 4 0 2 |LPM_ADD_SUB:6925|addcore:adder|:134
- 8 - G 17 OR2 1 3 0 3 |LPM_ADD_SUB:6925|addcore:adder|:143
- 6 - G 17 OR2 4 0 0 4 |LPM_ADD_SUB:6946|addcore:adder|:84
- 5 - G 17 AND2 0 3 0 3 |LPM_ADD_SUB:6946|addcore:adder|:95
- 2 - G 13 OR2 4 0 0 4 |LPM_ADD_SUB:6946|addcore:adder|:137
- 2 - G 17 OR2 1 3 0 3 |LPM_ADD_SUB:6968|addcore:adder|:99
- 3 - G 17 OR2 1 3 0 6 |LPM_ADD_SUB:6968|addcore:adder|:148
- 3 - G 07 OR2 0 3 0 3 |LPM_ADD_SUB:6968|addcore:adder|:149
- 1 - G 07 OR2 0 4 0 3 |LPM_ADD_SUB:6968|addcore:adder|:150
- 2 - G 07 OR2 0 4 0 2 |LPM_ADD_SUB:6968|addcore:adder|:151
- 1 - G 17 OR2 1 2 0 2 |LPM_ADD_SUB:6968|addcore:adder|:160
- 4 - G 03 AND2 1 2 0 3 |LPM_ADD_SUB:6991|addcore:adder|:107
- 5 - G 03 OR2 1 3 0 3 |LPM_ADD_SUB:7015|addcore:adder|pcarry3
- 3 - G 23 AND2 1 2 0 4 |LPM_ADD_SUB:7015|addcore:adder|:103
- 6 - G 03 OR2 2 2 0 1 |LPM_ADD_SUB:7015|addcore:adder|:109
- 4 - G 23 OR2 1 1 0 4 |LPM_ADD_SUB:7015|addcore:adder|:161
- 6 - G 23 OR2 1 2 0 3 |LPM_ADD_SUB:7015|addcore:adder|:163
- 2 - G 03 OR2 1 2 0 2 |LPM_ADD_SUB:7015|addcore:adder|:164
- 2 - G 25 OR2 0 3 0 4 |LPM_ADD_SUB:7015|addcore:adder|:166
- 3 - G 25 OR2 0 4 0 3 |LPM_ADD_SUB:7015|addcore:adder|:167
- 5 - G 25 OR2 0 4 0 2 |LPM_ADD_SUB:7015|addcore:adder|:168
- 7 - G 03 OR2 s 1 3 0 2 |LPM_ADD_SUB:7015|addcore:adder|~180~1
- 3 - G 03 OR2 2 2 0 4 |LPM_ADD_SUB:7040|addcore:adder|pcarry3
- 3 - L 02 AND2 1 2 0 3 |LPM_ADD_SUB:7040|addcore:adder|:107
- 8 - G 03 OR2 1 3 0 2 |LPM_ADD_SUB:7040|addcore:adder|:111
- 6 - G 22 AND2 0 3 0 2 |LPM_ADD_SUB:7040|addcore:adder|:123
- 2 - L 02 OR2 1 2 0 2 |LPM_ADD_SUB:7040|addcore:adder|:171
- 1 - G 03 OR2 2 2 0 3 |LPM_ADD_SUB:7040|addcore:adder|:189
- 2 - G 10 OR2 1 2 0 3 |LPM_ADD_SUB:7066|addcore:adder|pcarry3
- 4 - L 02 OR2 2 1 0 2 |LPM_ADD_SUB:7066|addcore:adder|:104
- 3 - G 10 OR2 0 4 0 2 |LPM_ADD_SUB:7066|addcore:adder|:115
- 5 - G 22 OR2 0 4 0 2 |LPM_ADD_SUB:7066|addcore:adder|:127
- 8 - G 23 OR2 3 1 0 3 |LPM_ADD_SUB:7066|addcore:adder|:177
- 7 - G 23 OR2 2 2 0 2 |LPM_ADD_SUB:7066|addcore:adder|:179
- 8 - G 10 OR2 0 4 0 2 |LPM_ADD_SUB:7066|addcore:adder|:180
- 8 - G 25 OR2 0 3 0 2 |LPM_ADD_SUB:7066|addcore:adder|:182
- 8 - G 22 OR2 0 4 0 2 |LPM_ADD_SUB:7066|addcore:adder|:183
- 6 - G 19 OR2 0 3 0 2 |LPM_ADD_SUB:7066|addcore:adder|:184
- 1 - G 04 OR2 s 1 1 0 2 |LPM_ADD_SUB:7066|addcore:adder|~198~1
- 5 - G 23 OR2 0 4 0 2 |LPM_ADD_SUB:7093|addcore:adder|pcarry1
- 5 - G 10 OR2 0 3 0 2 |LPM_ADD_SUB:7093|addcore:adder|pcarry2
- 2 - G 05 OR2 0 4 0 2 |LPM_ADD_SUB:7093|addcore:adder|pcarry3
- 4 - G 25 OR2 0 3 0 2 |LPM_ADD_SUB:7093|addcore:adder|pcarry4
- 4 - G 22 OR2 0 3 0 2 |LPM_ADD_SUB:7093|addcore:adder|pcarry5
- 2 - G 23 OR2 0 4 0 7 |LPM_ADD_SUB:7093|addcore:adder|:205
- 1 - G 10 OR2 0 3 0 6 |LPM_ADD_SUB:7093|addcore:adder|:206
- 4 - G 05 OR2 0 4 0 4 |LPM_ADD_SUB:7093|addcore:adder|:207
- 7 - G 19 OR2 s 0 4 0 1 |LPM_ADD_SUB:7093|addcore:adder|~211~1
- 8 - G 19 OR2 0 4 0 1 |LPM_ADD_SUB:7093|addcore:adder|:211
- 6 - G 01 OR2 3 0 0 5 |LPM_ADD_SUB:7226|addcore:adder|:145
- 7 - G 01 OR2 4 0 0 3 |LPM_ADD_SUB:7226|addcore:adder|:147
- 5 - G 01 OR2 4 0 0 2 |LPM_ADD_SUB:7226|addcore:adder|:148
- 1 - G 13 OR2 4 0 0 4 |LPM_ADD_SUB:7226|addcore:adder|:149
- 1 - G 01 OR2 1 3 0 4 |LPM_ADD_SUB:7249|addcore:adder|:103
- 4 - G 01 OR2 1 1 0 2 |LPM_ADD_SUB:7249|addcore:adder|:153
- 2 - G 01 OR2 1 3 0 2 |LPM_ADD_SUB:7249|addcore:adder|:156
- 3 - G 01 OR2 1 2 0 2 |LPM_ADD_SUB:7249|addcore:adder|:169
- 5 - G 06 OR2 0 4 0 2 |LPM_ADD_SUB:7273|addcore:adder|pcarry1
- 3 - G 06 OR2 0 3 0 2 |LPM_ADD_SUB:7273|addcore:adder|pcarry2
- 4 - G 26 OR2 0 4 0 2 |LPM_ADD_SUB:7273|addcore:adder|pcarry3
- 5 - G 26 OR2 0 4 0 2 |LPM_ADD_SUB:7273|addcore:adder|pcarry4
- 8 - G 01 OR2 1 2 1 0 |LPM_ADD_SUB:7273|addcore:adder|:161
- 6 - G 06 OR2 0 4 0 4 |LPM_ADD_SUB:7273|addcore:adder|:178
- 8 - G 06 OR2 0 3 0 3 |LPM_ADD_SUB:7273|addcore:adder|:179
- 1 - G 26 OR2 0 4 0 2 |LPM_ADD_SUB:7273|addcore:adder|:180
- 8 - G 26 OR2 s 0 3 0 1 |LPM_ADD_SUB:7273|addcore:adder|~181~1
- 7 - G 26 OR2 0 4 0 1 |LPM_ADD_SUB:7273|addcore:adder|:184
- 1 - C 24 OR2 ! 2 0 0 1 |LPM_ADD_SUB:7363|addcore:adder|:85
- 6 - C 02 AND2 1 1 0 5 |LPM_ADD_SUB:7384|addcore:adder|:84
- 8 - C 02 OR2 1 1 1 0 |LPM_ADD_SUB:7384|addcore:adder|:137
- 1 - C 13 OR2 2 1 0 4 |LPM_ADD_SUB:7384|addcore:adder|:139
- 2 - C 02 OR2 3 1 0 3 |LPM_ADD_SUB:7384|addcore:adder|:140
- 4 - C 13 OR2 s 3 1 0 3 |LPM_ADD_SUB:7384|addcore:adder|~141~1
- 4 - L 09 OR2 0 2 0 1 |LPM_ADD_SUB:7630|addcore:adder|:108
- 7 - L 17 OR2 0 3 0 1 |LPM_ADD_SUB:7630|addcore:adder|:109
- 5 - L 17 OR2 0 3 0 1 |LPM_ADD_SUB:7864|addcore:adder|:109
- 7 - G 05 OR2 0 3 0 1 |LPM_ADD_SUB:9059|addcore:adder|:109
- 7 - C 13 OR2 1 3 0 1 |LPM_ADD_SUB:10191|addcore:adder|:109
- 1 - L 09 AND2 s 0 3 0 2 ~7456~1
- 7 - L 09 OR2 s 0 4 0 1 ~7573~1
- 8 - L 06 OR2 ! 0 3 0 1 :7690
- 8 - L 08 OR2 ! 0 4 0 5 :7793
- 5 - L 08 AND2 ! 0 2 0 4 :7910
- 2 - L 08 OR2 ! 0 4 0 2 :7912
- 1 - L 08 OR2 ! 0 4 0 4 :8027
- 3 - L 06 OR2 s 0 2 0 3 ~8029~1
- 3 - L 08 OR2 ! 0 4 0 1 :8051
- 3 - L 17 OR2 0 4 0 1 :8184
- 4 - L 17 OR2 0 4 0 1 :8274
- 2 - L 17 OR2 0 4 0 1 :8280
- 6 - L 08 OR2 0 3 0 1 :8430
- 2 - L 06 OR2 0 3 0 12 :8453
- 1 - L 07 OR2 0 4 0 1 :8490
- 6 - L 17 OR2 0 4 0 1 :8502
- 6 - L 09 OR2 0 4 0 1 :8508
- 4 - L 06 OR2 0 4 0 12 :8599
- 8 - L 17 OR2 0 3 0 1 :8648
- 8 - L 09 OR2 0 4 0 1 :8654
- 7 - L 08 OR2 0 4 0 1 :8714
- 1 - L 06 OR2 0 4 0 11 :8745
- 1 - L 22 OR2 ! 0 4 0 6 :8746
- 7 - L 06 OR2 0 4 0 4 :8752
- 7 - L 11 OR2 0 4 0 4 :8758
- 1 - L 11 OR2 0 3 0 5 :8764
- 5 - L 11 AND2 0 2 0 4 :8770
- 2 - L 09 OR2 0 4 0 4 :8776
- 3 - L 09 OR2 0 4 0 3 :8782
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?