btobcd.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 970 行 · 第 1/5 页
RPT
970 行
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | RESERVED
RESERVED | 44 113 | BCD12
CINA3 | 45 112 | BCD11
CINA2 | 46 111 | CINA1
CINA0 | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R R R R G R R R R R R V R R R R R V R R R G V C C C G G R V R R R R C R V R R R R B R V R B R R B R
E E E E E E N E E E E E E C E E E E E C E E E N C I I I N N E C E E E E I E C E E E E C E C E C E E C E
S S S S S S D S S S S S S C S S S S S C S S S D C N N N D D S C S S S S N S C S S S S D S C S D S S D S
E E E E E E E E E E E E I E E E E E I E E E I A A A E I E E E E A E I E E E E 1 E I E 3 E E 3 E
R R R R R R R R R R R R O R R R R R N R R R N 1 9 1 R O R R R R 7 R N R R R R 0 R O R 1 R R 0 R
V V V V V V V V V V V V V V V V V T V V V T 4 3 V V V V V V T V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\cal\btobcd.rpt
btobcd
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/26( 23%)
C13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/26( 30%)
C24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
G1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 6/26( 23%)
G2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/26( 26%)
G3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
G4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
G5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
G6 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/26( 30%)
G7 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 4/26( 15%)
G10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 14/26( 53%)
G13 5/ 8( 62%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
G16 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 6/26( 23%)
G17 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
G18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
G19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/26( 34%)
G22 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/26( 26%)
G23 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
G25 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/26( 34%)
G26 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
L2 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 12/26( 46%)
L4 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 8/26( 30%)
L5 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 9/26( 34%)
L6 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 11/26( 42%)
L7 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 8/26( 30%)
L8 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/26( 46%)
L9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 9/26( 34%)
L11 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
L14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/26( 23%)
L16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
L17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 9/26( 34%)
L22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
L25 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/26( 26%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 25/141 ( 17%)
Total logic cells used: 232/4992 ( 4%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.39/4 ( 84%)
Total fan-in: 788/19968 ( 3%)
Total input pins required: 15
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 232
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 28/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 8 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 8 8 8 1 8 8 7 0 0 8 0 0 5 0 0 8 8 1 8 0 0 8 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 8 0 8 8 8 8 8 8 0 8 0 0 8 0 8 8 0 0 0 0 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 97/0
Total: 8 24 8 9 16 16 15 8 8 8 8 0 13 8 0 16 16 1 8 0 0 9 8 1 16 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 232/0
Device-Specific Information: e:\cal\btobcd.rpt
btobcd
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
47 - - L -- INPUT ^ 0 0 0 1 CINA0
111 - - L -- INPUT ^ 0 0 0 5 CINA1
46 - - L -- INPUT ^ 0 0 0 4 CINA2
45 - - L -- INPUT ^ 0 0 0 2 CINA3
167 - - - 16 INPUT ^ 0 0 0 10 CINA4
160 - - - 12 INPUT ^ 0 0 0 9 CINA5
158 - - - 10 INPUT ^ 0 0 0 7 CINA6
89 - - - 18 INPUT ^ 0 0 0 11 CINA7
183 - - - -- INPUT ^ 0 0 0 11 CINA8
79 - - - -- INPUT ^ 0 0 0 14 CINA9
159 - - - 11 INPUT ^ 0 0 0 7 CINA10
182 - - - -- INPUT ^ 0 0 0 17 CINA11
184 - - - -- INPUT ^ 0 0 0 14 CINA12
80 - - - -- INPUT ^ 0 0 0 19 CINA13
78 - - - -- INPUT ^ 0 0 0 18 CINA14
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\btobcd.rpt
btobcd
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
96 - - - 08 OUTPUT 0 1 0 0 BCD10
112 - - L -- OUTPUT 0 1 0 0 BCD11
113 - - K -- OUTPUT 0 1 0 0 BCD12
168 - - - 17 OUTPUT 0 1 0 0 BCD13
122 - - G -- OUTPUT 0 1 0 0 BCD20
29 - - G -- OUTPUT 0 1 0 0 BCD21
166 - - - 15 OUTPUT 0 1 0 0 BCD22
121 - - G -- OUTPUT 0 1 0 0 BCD23
103 - - - 02 OUTPUT 0 1 0 0 BCD30
100 - - - 05 OUTPUT 0 1 0 0 BCD31
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