control3.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 528 行 · 第 1/3 页
RPT
528 行
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Device-Specific Information: e:\cal\control3.rpt
control3
** EQUATIONS **
outcode0 : INPUT;
outcode1 : INPUT;
outcode2 : INPUT;
outcode3 : INPUT;
-- Node name is 'add' from file "control3.tdf" line 16, column 7
-- Equation name is 'add', type is output
add = !_LC2_A3;
-- Node name is 'dic' from file "control3.tdf" line 19, column 7
-- Equation name is 'dic', type is output
dic = _LC6_A3;
-- Node name is 'mul' from file "control3.tdf" line 18, column 7
-- Equation name is 'mul', type is output
mul = !_LC4_A3;
-- Node name is 'sub' from file "control3.tdf" line 17, column 7
-- Equation name is 'sub', type is output
sub = !_LC1_A3;
-- Node name is ':39' from file "control3.tdf" line 7, column 16
-- Equation name is '_LC2_A3', type is buried
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ001);
_EQ001 = !outcode0 & outcode1 & !outcode2 & outcode3;
-- Node name is ':46' from file "control3.tdf" line 9, column 16
-- Equation name is '_LC1_A3', type is buried
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ002);
_EQ002 = outcode0 & outcode1 & !outcode2 & outcode3;
-- Node name is ':54' from file "control3.tdf" line 11, column 16
-- Equation name is '_LC4_A3', type is buried
!_LC4_A3 = _LC4_A3~NOT;
_LC4_A3~NOT = LCELL( _EQ003);
_EQ003 = !outcode0 & !outcode1 & outcode2 & outcode3;
-- Node name is ':65' from file "control3.tdf" line 13, column 1
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ004);
_EQ004 = outcode0 & !outcode1 & outcode2 & outcode3;
Project Information e:\cal\control3.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 56,217K
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