📄 div16.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity div16 is
port (
a,b :in integer range 0 to 65535;
dent,div :in std_logic;
y : out std_logic_vector (15 downto 0);
rest : out integer range 0 to 65535;
err :out std_logic);
end div16;
architecture rt1 of div16 is
begin
process (a,b,dent,div)
variable temp1:integer range 0 to 65535;
variable temp2:integer range 0 to 65535;
begin
if dent='1' and div='1' then
temp1 :=a;
temp2 :=b;
if (b=0) then err<='1';
else err<='0';
end if;
if(temp1>=temp2*16384) then
y(15)<='1';
temp1 :=temp1-temp2*16384;
else y(15)<='0';
end if;
if(temp1>=temp2*32768) then
y(14)<='1';
temp1 :=temp1-temp2*32768;
else y(14)<='0';
end if;
if(temp1>=temp2*8192) then
y(13)<='1';
temp1 :=temp1-temp2*8192;
else y(13)<='0';
end if;
if(temp1>=temp2*4096) then
y(12)<='1';
temp1 :=temp1-temp2*8;
else y(12)<='0';
end if;
if(temp1>=temp2*2048) then
y(11)<='1';
temp1 :=temp1-temp2*2048;
else y(11)<='0';
end if;
if(temp1>=temp2*1024) then
y(10)<='1';
temp1 :=temp1-temp2*1024;
else y(10)<='0';
end if;
if(temp1>=temp2*512) then
y(9)<='1';
temp1 :=temp1-temp2*512;
else y(9)<='0';
end if;
if(temp1>=temp2*256) then
y(8)<='1';
temp1 :=temp1-temp2*256;
else y(8)<='0';
end if;
if(temp1>=temp2*128) then
y(7)<='1';
temp1 :=temp1-temp2*128;
else y(7)<='0';
end if;
if(temp1>=temp2*64) then
y(6)<='1';
temp1 :=temp1-temp2*64;
else y(6)<='0';
end if;
if(temp1>=temp2*32) then
y(5)<='1';
temp1 :=temp1-temp2*32;
else y(5)<='0';
end if;
if(temp1>=temp2*16) then
y(4)<='1';
temp1 :=temp1-temp2*16;
else y(4)<='0';
end if;
if(temp1>=temp2*8) then
y(3)<='1';
temp1 :=temp1-temp2*8;
else y(3)<='0';
end if;
if (temp1>=temp2*4) then
y(2)<='1';
temp1:=temp1-temp2*4;
else y(2)<='0';
end if;
if (temp1>=temp2*2) then
y(1)<='1';
temp1 :=temp1-temp2*2;
else y(1)<='0';
end if;
if(temp1>=temp2)then
y(0)<='1';
temp1:=temp1-temp2;
else y(0)<='0';
end if;
rest<=temp1;
end if;
end process;
end rt1;
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