key2.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,294 行 · 第 1/5 页

         #  _LC8_I33;

-- Node name is '~1468~1' 
-- Equation name is '~1468~1', location is LC1_I52, type is buried.
-- synthesized logic cell 
!_LC1_I52 = _LC1_I52~NOT;
_LC1_I52~NOT = LCELL( _EQ061);
  _EQ061 = !_LC1_I33 & !_LC2_I33 & !_LC3_I33 & !_LC8_I33;

-- Node name is ':1880' 
-- Equation name is '_LC2_I37', type is buried 
!_LC2_I37 = _LC2_I37~NOT;
_LC2_I37~NOT = LCELL( _EQ062);
  _EQ062 = !keyout7
         # !keyout6
         #  keyout4 &  keyout5
         # !keyout4 & !keyout5;

-- Node name is ':1990' 
-- Equation name is '_LC6_I37', type is buried 
_LC6_I37 = LCELL( _EQ063);
  _EQ063 =  keyout4 &  keyout5 &  keyout6 & !keyout7;

-- Node name is ':2026' 
-- Equation name is '_LC3_I37', type is buried 
_LC3_I37 = LCELL( _EQ064);
  _EQ064 = !keyout4 &  keyout5 &  keyout6 &  keyout7;

-- Node name is ':2041' 
-- Equation name is '_LC4_I37', type is buried 
_LC4_I37 = LCELL( _EQ065);
  _EQ065 =  keyout4 &  keyout5 &  keyout6 & !keyout7
         #  keyout4 & !keyout5 &  keyout6 &  keyout7;

-- Node name is ':2330' 
-- Equation name is '_LC1_I37', type is buried 
_LC1_I37 = LCELL( _EQ066);
  _EQ066 =  keyout4 &  keyout5 & !keyout6 &  keyout7;

-- Node name is ':2426' 
-- Equation name is '_LC1_I46', type is buried 
_LC1_I46 = LCELL( _EQ067);
  _EQ067 =  keyout0 &  keyout1 &  keyout2 & !keyout3;

-- Node name is ':2438' 
-- Equation name is '_LC4_I46', type is buried 
_LC4_I46 = LCELL( _EQ068);
  _EQ068 =  keyout0 &  keyout1 & !keyout2 &  keyout3;

-- Node name is ':2450' 
-- Equation name is '_LC2_I46', type is buried 
!_LC2_I46 = _LC2_I46~NOT;
_LC2_I46~NOT = LCELL( _EQ069);
  _EQ069 = !keyout3
         # !keyout2
         # !keyout0
         #  keyout1;

-- Node name is '~2462~1' 
-- Equation name is '~2462~1', location is LC1_I44, type is buried.
-- synthesized logic cell 
_LC1_I44 = LCELL( _EQ070);
  _EQ070 = !_LC2_I46 &  _LC4_I46;

-- Node name is ':2462' 
-- Equation name is '_LC3_I46', type is buried 
_LC3_I46 = LCELL( _EQ071);
  _EQ071 = !keyout0 &  keyout1 &  keyout2 &  keyout3;

-- Node name is '~2467~1' 
-- Equation name is '~2467~1', location is LC6_I30, type is buried.
-- synthesized logic cell 
_LC6_I30 = LCELL( _EQ072);
  _EQ072 = !_LC2_I46 &  _LC4_I37
         #  _LC1_I37 & !_LC2_I46
         #  _LC3_I37;

-- Node name is '~2467~2' 
-- Equation name is '~2467~2', location is LC7_I30, type is buried.
-- synthesized logic cell 
_LC7_I30 = LCELL( _EQ073);
  _EQ073 =  _LC2_I46 &  _LC6_I37
         #  _LC2_I46 &  _LC3_I37
         #  _LC4_I46 &  _LC6_I37
         #  _LC3_I37 &  _LC4_I46;

-- Node name is ':2467' 
-- Equation name is '_LC8_I30', type is buried 
_LC8_I30 = LCELL( _EQ074);
  _EQ074 =  _LC1_I46 & !_LC3_I46 &  _LC6_I30
         # !_LC3_I46 &  _LC7_I30;

-- Node name is '~2480~1' 
-- Equation name is '~2480~1', location is LC5_I37, type is buried.
-- synthesized logic cell 
_LC5_I37 = LCELL( _EQ075);
  _EQ075 =  keyout4 &  keyout5 &  keyout6 & !keyout7
         #  keyout4 &  keyout5 & !keyout6 &  keyout7;

-- Node name is '~2480~2' 
-- Equation name is '~2480~2', location is LC7_I46, type is buried.
-- synthesized logic cell 
_LC7_I46 = LCELL( _EQ076);
  _EQ076 =  _LC1_I46 &  _LC5_I37
         #  _LC4_I37 &  _LC4_I46;

-- Node name is '~2480~3' 
-- Equation name is '~2480~3', location is LC8_I46, type is buried.
-- synthesized logic cell 
_LC8_I46 = LCELL( _EQ077);
  _EQ077 = !_LC2_I46 & !_LC3_I37 &  _LC7_I46
         #  _LC2_I46 & !_LC3_I37 &  _LC4_I37;

-- Node name is ':2480' 
-- Equation name is '_LC6_I46', type is buried 
_LC6_I46 = LCELL( _EQ078);
  _EQ078 = !_LC3_I46 &  _LC8_I46
         #  _LC2_I37 &  _LC3_I46;

-- Node name is ':2490' 
-- Equation name is '_LC3_I30', type is buried 
_LC3_I30 = LCELL( _EQ079);
  _EQ079 = !_LC3_I37 &  _LC4_I37 &  _LC4_I46
         #  _LC1_I37 & !_LC3_I37 &  _LC4_I46;

-- Node name is ':2493' 
-- Equation name is '_LC5_I30', type is buried 
_LC5_I30 = LCELL( _EQ080);
  _EQ080 = !_LC2_I37 &  _LC2_I46 &  _LC6_I37
         #  _LC1_I37 & !_LC2_I37 &  _LC2_I46;

-- Node name is ':2494' 
-- Equation name is '_LC4_I30', type is buried 
_LC4_I30 = LCELL( _EQ081);
  _EQ081 =  _LC1_I46 &  _LC2_I37 & !_LC2_I46
         # !_LC2_I46 &  _LC3_I30;

-- Node name is ':2495' 
-- Equation name is '_LC1_I30', type is buried 
_LC1_I30 = LCELL( _EQ082);
  _EQ082 = !_LC3_I46 &  _LC4_I30
         # !_LC3_I46 &  _LC5_I30
         #  _LC3_I37 &  _LC3_I46;

-- Node name is '~2510~1' 
-- Equation name is '~2510~1', location is LC2_I30, type is buried.
-- synthesized logic cell 
_LC2_I30 = LCELL( _EQ083);
  _EQ083 =  _LC2_I46 & !_LC3_I37 &  _LC4_I37
         #  _LC1_I46 & !_LC3_I37 &  _LC4_I37;

-- Node name is '~2510~2' 
-- Equation name is '~2510~2', location is LC7_I37, type is buried.
-- synthesized logic cell 
_LC7_I37 = LCELL( _EQ084);
  _EQ084 =  _LC1_I37
         #  _LC3_I37;

-- Node name is ':2510' 
-- Equation name is '_LC7_I44', type is buried 
_LC7_I44 = LCELL( _EQ085);
  _EQ085 =  _LC2_I30 & !_LC3_I46
         #  _LC3_I46 &  _LC7_I37
         #  _LC1_I44 &  _LC7_I37;



Project Information                                            e:\cal\key2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 53,981K