key2.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,294 行 · 第 1/5 页
RPT
1,294 行
Device-Specific Information: e:\cal\key2.rpt
key2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G ^ 0 0 0 0 inclk
184 - - - -- INPUT ^ 0 0 0 1 inkey0
182 - - - -- INPUT ^ 0 0 0 1 inkey1
80 - - - -- INPUT ^ 0 0 0 1 inkey2
78 - - - -- INPUT ^ 0 0 0 1 inkey3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cal\key2.rpt
key2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
197 - - - 43 OUTPUT 0 1 0 0 outcode0
189 - - - 30 OUTPUT 0 1 0 0 outcode1
200 - - - 46 OUTPUT 0 1 0 0 outcode2
116 - - I -- OUTPUT 0 1 0 0 outcode3
67 - - - 33 OUTPUT 0 1 0 0 outkey0
68 - - - 33 OUTPUT 0 1 0 0 outkey1
190 - - - 33 OUTPUT 0 1 0 0 outkey2
38 - - I -- OUTPUT 0 1 0 0 outkey3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\key2.rpt
key2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 40 AND2 0 3 0 5 |LPM_ADD_SUB:256|addcore:adder|:111
- 8 - B 42 AND2 0 2 0 1 |LPM_ADD_SUB:256|addcore:adder|:115
- 5 - B 42 AND2 0 3 0 2 |LPM_ADD_SUB:256|addcore:adder|:119
- 7 - B 42 AND2 0 3 0 2 |LPM_ADD_SUB:256|addcore:adder|:127
- 2 - B 42 AND2 0 2 0 3 |LPM_ADD_SUB:256|addcore:adder|:131
- 3 - B 33 AND2 0 3 0 3 |LPM_ADD_SUB:256|addcore:adder|:139
- 1 - B 33 AND2 0 3 0 3 |LPM_ADD_SUB:256|addcore:adder|:147
- 2 - B 48 AND2 0 3 0 3 |LPM_ADD_SUB:256|addcore:adder|:155
- 6 - B 48 AND2 0 2 0 1 |LPM_ADD_SUB:256|addcore:adder|:159
- 1 - I 27 DFFE 1 1 0 2 |tinglmove:movskipX|:1
- 1 - I 36 DFFE 0 2 0 2 |tinglmove:movskipX|:2
- 8 - I 43 DFFE 0 2 0 1 |tinglmove:movskipX|:3
- 3 - I 43 DFFE 0 4 0 2 |tinglmove:movskipX|b (|tinglmove:movskipX|:13)
- 5 - I 41 DFFE 1 1 0 2 |tinglmove:movskipX~45|:1
- 6 - I 41 DFFE 0 2 0 2 |tinglmove:movskipX~45|:2
- 7 - I 41 DFFE 0 2 0 1 |tinglmove:movskipX~45|:3
- 8 - I 41 DFFE 0 4 0 2 |tinglmove:movskipX~45|b (|tinglmove:movskipX~45|:13)
- 8 - I 36 DFFE 1 1 0 2 |tinglmove:movskipX~61|:1
- 2 - I 36 DFFE 0 2 0 2 |tinglmove:movskipX~61|:2
- 1 - I 41 DFFE 0 2 0 1 |tinglmove:movskipX~61|:3
- 4 - I 36 DFFE 0 4 0 2 |tinglmove:movskipX~61|b (|tinglmove:movskipX~61|:13)
- 5 - I 43 DFFE 1 1 0 2 |tinglmove:movskipX~73|:1
- 6 - I 43 DFFE 0 2 0 2 |tinglmove:movskipX~73|:2
- 7 - I 43 DFFE 0 2 0 1 |tinglmove:movskipX~73|:3
- 4 - I 43 DFFE 0 4 0 2 |tinglmove:movskipX~73|b (|tinglmove:movskipX~73|:13)
- 6 - B 40 DFFE + 0 1 0 20 keyclkout (:15)
- 7 - B 48 DFFE + 0 3 0 1 keyclk16 (:43)
- 5 - B 48 DFFE + 0 3 0 2 keyclk15 (:44)
- 4 - B 48 DFFE + 0 2 0 3 keyclk14 (:45)
- 8 - B 48 DFFE + 0 3 0 2 keyclk13 (:46)
- 3 - B 40 DFFE + 0 2 0 3 keyclk12 (:47)
- 6 - B 33 DFFE + 0 3 0 2 keyclk11 (:48)
- 5 - B 33 DFFE + 0 2 0 3 keyclk10 (:49)
- 4 - B 33 DFFE + 0 3 0 2 keyclk9 (:50)
- 7 - B 33 DFFE + 0 2 0 3 keyclk8 (:51)
- 1 - B 42 DFFE + 0 2 0 2 keyclk7 (:52)
- 6 - B 42 DFFE + 0 3 0 2 keyclk6 (:53)
- 3 - B 42 DFFE + 0 3 0 3 keyclk5 (:54)
- 4 - B 42 DFFE + 0 3 0 3 keyclk4 (:55)
- 8 - B 40 DFFE + 0 2 0 4 keyclk3 (:56)
- 7 - B 40 DFFE + 0 3 0 1 keyclk2 (:57)
- 4 - B 40 DFFE + 0 2 0 2 keyclk1 (:58)
- 5 - B 40 DFFE + 0 0 0 3 keyclk0 (:59)
- 6 - I 36 DFFE 0 3 0 2 chuclk2 (:60)
- 5 - I 36 DFFE 0 2 0 3 chuclk1 (:61)
- 7 - I 36 DFFE 0 3 0 3 chuclk0 (:62)
- 3 - I 36 DFFE 0 4 0 12 chuclkout (:63)
- 5 - I 33 DFFE 0 4 1 6 chuout0 (:64)
- 6 - I 33 DFFE 0 4 1 6 chuout1 (:65)
- 7 - I 33 DFFE 0 4 1 6 chuout2 (:66)
- 8 - I 52 DFFE 0 4 1 7 chuout3 (:67)
- 5 - I 46 DFFE 0 4 0 4 keyout0 (:68)
- 5 - I 52 DFFE 0 5 0 5 keyout1 (:69)
- 4 - I 33 DFFE 0 5 0 5 keyout2 (:70)
- 4 - I 52 DFFE 0 4 0 4 keyout3 (:71)
- 1 - I 43 DFFE 0 4 0 6 keyout4 (:72)
- 2 - I 41 DFFE 0 4 0 6 keyout5 (:73)
- 3 - I 41 DFFE 0 4 0 6 keyout6 (:74)
- 2 - I 43 DFFE 0 4 0 6 keyout7 (:75)
- 3 - B 48 OR2 s 0 3 0 1 ~145~1
- 2 - B 33 OR2 s 0 4 0 1 ~145~2
- 8 - B 33 OR2 s 0 4 0 1 ~145~3
- 1 - B 48 OR2 s 0 4 0 1 ~145~4
- 2 - B 40 OR2 ! 0 4 0 17 :145
- 2 - I 33 OR2 ! 0 4 0 6 :764
- 8 - I 33 OR2 ! 0 4 0 6 :773
- 3 - I 33 OR2 ! 0 4 0 6 :782
- 1 - I 33 OR2 ! 0 4 0 5 :791
- 4 - I 41 AND2 0 4 0 10 :805
- 3 - I 52 OR2 s 0 3 0 1 ~1363~1
- 6 - I 52 OR2 s 0 4 0 1 ~1378~1
- 2 - I 52 OR2 s 0 4 0 1 ~1393~1
- 7 - I 52 OR2 s 0 3 0 1 ~1408~1
- 1 - I 52 AND2 s ! 0 4 0 4 ~1468~1
- 2 - I 37 OR2 ! 0 4 0 3 :1880
- 6 - I 37 AND2 0 4 0 2 :1990
- 3 - I 37 AND2 0 4 0 7 :2026
- 4 - I 37 OR2 0 4 0 5 :2041
- 1 - I 37 AND2 0 4 0 4 :2330
- 1 - I 46 AND2 0 4 0 4 :2426
- 4 - I 46 AND2 0 4 0 4 :2438
- 2 - I 46 OR2 ! 0 4 0 7 :2450
- 1 - I 44 AND2 s 0 2 0 1 ~2462~1
- 3 - I 46 AND2 0 4 0 4 :2462
- 6 - I 30 OR2 s 0 4 0 1 ~2467~1
- 7 - I 30 OR2 s 0 4 0 1 ~2467~2
- 8 - I 30 OR2 0 4 1 0 :2467
- 5 - I 37 OR2 s 0 4 0 1 ~2480~1
- 7 - I 46 OR2 s 0 4 0 1 ~2480~2
- 8 - I 46 OR2 s 0 4 0 1 ~2480~3
- 6 - I 46 OR2 0 3 1 0 :2480
- 3 - I 30 OR2 0 4 0 1 :2490
- 5 - I 30 OR2 0 4 0 1 :2493
- 4 - I 30 OR2 0 4 0 1 :2494
- 1 - I 30 OR2 0 4 1 0 :2495
- 2 - I 30 OR2 s 0 4 0 1 ~2510~1
- 7 - I 37 OR2 s 0 2 0 1 ~2510~2
- 7 - I 44 OR2 0 4 1 0 :2510
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\key2.rpt
key2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 13/208( 6%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 14/208( 6%) 0/104( 0%) 24/104( 23%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?