reg1.rpt

ProtelDXp 实现计算器功能

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Device-Specific Information:                                   e:\cal\reg1.rpt
reg1

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        4         CLK


Device-Specific Information:                                   e:\cal\reg1.rpt
reg1

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         CLRN


Device-Specific Information:                                   e:\cal\reg1.rpt
reg1

** EQUATIONS **

CLK      : INPUT;
CLRN     : INPUT;
D0       : INPUT;
D1       : INPUT;
D2       : INPUT;
D3       : INPUT;

-- Node name is 'Q0' 
-- Equation name is 'Q0', type is output 
Q0       =  _LC1_D15;

-- Node name is 'Q1' 
-- Equation name is 'Q1', type is output 
Q1       =  _LC1_C20;

-- Node name is 'Q2' 
-- Equation name is 'Q2', type is output 
Q2       =  _LC8_L44;

-- Node name is 'Q3' 
-- Equation name is 'Q3', type is output 
Q3       =  _LC3_F39;

-- Node name is ':1' 
-- Equation name is '_LC1_D15', type is buried 
_LC1_D15 = DFFE( D0, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);

-- Node name is ':3' 
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = DFFE( D1, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);

-- Node name is ':4' 
-- Equation name is '_LC8_L44', type is buried 
_LC8_L44 = DFFE( D2, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);

-- Node name is ':5' 
-- Equation name is '_LC3_F39', type is buried 
_LC3_F39 = DFFE( D3, GLOBAL( CLK), GLOBAL( CLRN),  VCC,  VCC);



Project Information                                            e:\cal\reg1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,663K