control2.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,076 行 · 第 1/4 页

-- Node name is ':236' from file "control2.tdf" line 27, column 7
-- Equation name is '_LC6_D30', type is buried 
_LC6_D30 = LCELL( _EQ028);
  _EQ028 =  _LC7_D30
         #  diva3 &  _LC2_F29
         #  _LC8_D30;

-- Node name is '~238~1' from file "control2.tdf" line 28, column 7
-- Equation name is '~238~1', location is LC2_K31, type is buried.
-- synthesized logic cell 
_LC2_K31 = LCELL( _EQ029);
  _EQ029 = !_LC2_H43 &  muxb0
         # !_LC1_H43 &  subb0;

-- Node name is ':238' from file "control2.tdf" line 28, column 7
-- Equation name is '_LC7_K31', type is buried 
_LC7_K31 = LCELL( _EQ030);
  _EQ030 =  _LC1_K31
         #  divb0 &  _LC2_F29
         #  _LC2_K31;

-- Node name is '~240~1' from file "control2.tdf" line 28, column 7
-- Equation name is '~240~1', location is LC4_K31, type is buried.
-- synthesized logic cell 
_LC4_K31 = LCELL( _EQ031);
  _EQ031 = !_LC2_H43 &  muxb1
         # !_LC1_H43 &  subb1;

-- Node name is ':240' from file "control2.tdf" line 28, column 7
-- Equation name is '_LC5_K31', type is buried 
_LC5_K31 = LCELL( _EQ032);
  _EQ032 =  _LC3_K31
         #  divb1 &  _LC2_F29
         #  _LC4_K31;

-- Node name is '~242~1' from file "control2.tdf" line 28, column 7
-- Equation name is '~242~1', location is LC6_K31, type is buried.
-- synthesized logic cell 
_LC6_K31 = LCELL( _EQ033);
  _EQ033 = !_LC2_H43 &  muxb2
         # !_LC1_H43 &  subb2;

-- Node name is ':242' from file "control2.tdf" line 28, column 7
-- Equation name is '_LC8_K31', type is buried 
_LC8_K31 = LCELL( _EQ034);
  _EQ034 =  _LC1_K48
         #  divb2 &  _LC2_F29
         #  _LC6_K31;

-- Node name is '~244~1' from file "control2.tdf" line 28, column 7
-- Equation name is '~244~1', location is LC4_A28, type is buried.
-- synthesized logic cell 
_LC4_A28 = LCELL( _EQ035);
  _EQ035 = !_LC2_H43 &  muxb3
         # !_LC1_H43 &  subb3;

-- Node name is ':244' from file "control2.tdf" line 28, column 7
-- Equation name is '_LC3_A28', type is buried 
_LC3_A28 = LCELL( _EQ036);
  _EQ036 =  _LC1_A28
         #  divb3 &  _LC2_F29
         #  _LC4_A28;

-- Node name is '~246~1' from file "control2.tdf" line 29, column 7
-- Equation name is '~246~1', location is LC5_D30, type is buried.
-- synthesized logic cell 
_LC5_D30 = LCELL( _EQ037);
  _EQ037 = !_LC2_H43 &  muxc0
         # !_LC1_H43 &  subc0;

-- Node name is ':246' from file "control2.tdf" line 29, column 7
-- Equation name is '_LC3_D30', type is buried 
_LC3_D30 = LCELL( _EQ038);
  _EQ038 =  _LC3_K48
         #  divc0 &  _LC2_F29
         #  _LC5_D30;

-- Node name is '~248~1' from file "control2.tdf" line 29, column 7
-- Equation name is '~248~1', location is LC4_C36, type is buried.
-- synthesized logic cell 
_LC4_C36 = LCELL( _EQ039);
  _EQ039 = !_LC2_H43 &  muxc1
         # !_LC1_H43 &  subc1;

-- Node name is ':248' from file "control2.tdf" line 29, column 7
-- Equation name is '_LC1_C36', type is buried 
_LC1_C36 = LCELL( _EQ040);
  _EQ040 =  _LC3_C36
         #  divc1 &  _LC2_F29
         #  _LC4_C36;

-- Node name is '~250~1' from file "control2.tdf" line 29, column 7
-- Equation name is '~250~1', location is LC5_C36, type is buried.
-- synthesized logic cell 
_LC5_C36 = LCELL( _EQ041);
  _EQ041 = !_LC2_H43 &  muxc2
         # !_LC1_H43 &  subc2;

-- Node name is ':250' from file "control2.tdf" line 29, column 7
-- Equation name is '_LC6_C36', type is buried 
_LC6_C36 = LCELL( _EQ042);
  _EQ042 =  _LC2_K48
         #  divc2 &  _LC2_F29
         #  _LC5_C36;

-- Node name is '~252~1' from file "control2.tdf" line 29, column 7
-- Equation name is '~252~1', location is LC8_C36, type is buried.
-- synthesized logic cell 
_LC8_C36 = LCELL( _EQ043);
  _EQ043 = !_LC2_H43 &  muxc3
         # !_LC1_H43 &  subc3;

-- Node name is ':252' from file "control2.tdf" line 29, column 7
-- Equation name is '_LC2_C36', type is buried 
_LC2_C36 = LCELL( _EQ044);
  _EQ044 =  _LC7_C36
         #  divc3 &  _LC2_F29
         #  _LC8_C36;

-- Node name is '~254~1' from file "control2.tdf" line 30, column 7
-- Equation name is '~254~1', location is LC5_F29, type is buried.
-- synthesized logic cell 
_LC5_F29 = LCELL( _EQ045);
  _EQ045 = !_LC2_H43 &  muxd0
         # !_LC1_H43 &  subd0;

-- Node name is ':254' from file "control2.tdf" line 30, column 7
-- Equation name is '_LC6_F29', type is buried 
_LC6_F29 = LCELL( _EQ046);
  _EQ046 =  _LC4_F29
         #  divd0 &  _LC2_F29
         #  _LC5_F29;

-- Node name is '~256~1' from file "control2.tdf" line 30, column 7
-- Equation name is '~256~1', location is LC8_F29, type is buried.
-- synthesized logic cell 
_LC8_F29 = LCELL( _EQ047);
  _EQ047 = !_LC2_H43 &  muxd1
         # !_LC1_H43 &  subd1;

-- Node name is ':256' from file "control2.tdf" line 30, column 7
-- Equation name is '_LC3_F29', type is buried 
_LC3_F29 = LCELL( _EQ048);
  _EQ048 =  _LC7_F29
         #  divd1 &  _LC2_F29
         #  _LC8_F29;

-- Node name is '~258~1' from file "control2.tdf" line 30, column 7
-- Equation name is '~258~1', location is LC1_F29, type is buried.
-- synthesized logic cell 
_LC1_F29 = LCELL( _EQ049);
  _EQ049 = !_LC2_H43 &  muxd2
         # !_LC1_H43 &  subd2;

-- Node name is ':258' from file "control2.tdf" line 30, column 7
-- Equation name is '_LC5_H43', type is buried 
_LC5_H43 = LCELL( _EQ050);
  _EQ050 =  _LC4_H43
         #  divd2 &  _LC2_F29
         #  _LC1_F29;

-- Node name is '~260~1' from file "control2.tdf" line 30, column 7
-- Equation name is '~260~1', location is LC4_D30, type is buried.
-- synthesized logic cell 
_LC4_D30 = LCELL( _EQ051);
  _EQ051 = !_LC2_H43 &  muxd3
         # !_LC1_H43 &  subd3;

-- Node name is ':260' from file "control2.tdf" line 30, column 7
-- Equation name is '_LC2_D30', type is buried 
_LC2_D30 = LCELL( _EQ052);
  _EQ052 =  _LC1_D30
         #  divd3 &  _LC2_F29
         #  _LC4_D30;



Project Information                                        e:\cal\control2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 53,354K