control2.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,076 行 · 第 1/4 页
RPT
1,076 行
200 - - - 46 INPUT ^ 0 0 0 1 divc2
139 - - C -- INPUT ^ 0 0 0 1 divc3
183 - - - -- INPUT ^ 0 0 0 1 divd0
27 - - F -- INPUT ^ 0 0 0 1 divd1
36 - - H -- INPUT ^ 0 0 0 1 divd2
134 - - D -- INPUT ^ 0 0 0 1 divd3
7 - - A -- INPUT ^ 0 0 0 1 muxa0
150 - - A -- INPUT ^ 0 0 0 1 muxa1
195 - - - 39 INPUT ^ 0 0 0 1 muxa2
60 - - - 40 INPUT ^ 0 0 0 1 muxa3
56 - - - 45 INPUT ^ 0 0 0 1 muxb0
190 - - - 33 INPUT ^ 0 0 0 1 muxb1
53 - - - 52 INPUT ^ 0 0 0 1 muxb2
203 - - - 48 INPUT ^ 0 0 0 1 muxb3
133 - - D -- INPUT ^ 0 0 0 1 muxc0
168 - - - 17 INPUT ^ 0 0 0 1 muxc1
196 - - - 41 INPUT ^ 0 0 0 1 muxc2
140 - - C -- INPUT ^ 0 0 0 1 muxc3
126 - - F -- INPUT ^ 0 0 0 1 muxd0
204 - - - 49 INPUT ^ 0 0 0 1 muxd1
61 - - - 40 INPUT ^ 0 0 0 1 muxd2
68 - - - 33 INPUT ^ 0 0 0 1 muxd3
10 - - A -- INPUT ^ 0 0 0 1 suba0
58 - - - 42 INPUT ^ 0 0 0 1 suba1
120 - - H -- INPUT ^ 0 0 0 1 suba2
191 - - - 35 INPUT ^ 0 0 0 1 suba3
57 - - - 43 INPUT ^ 0 0 0 1 subb0
54 - - - 51 INPUT ^ 0 0 0 1 subb1
44 - - K -- INPUT ^ 0 0 0 1 subb2
64 - - - 35 INPUT ^ 0 0 0 1 subb3
55 - - - 48 INPUT ^ 0 0 0 1 subc0
193 - - - 38 INPUT ^ 0 0 0 1 subc1
202 - - - 47 INPUT ^ 0 0 0 1 subc2
198 - - - 44 INPUT ^ 0 0 0 1 subc3
69 - - - 32 INPUT ^ 0 0 0 1 subd0
70 - - - 31 INPUT ^ 0 0 0 1 subd1
127 - - F -- INPUT ^ 0 0 0 1 subd2
187 - - - 28 INPUT ^ 0 0 0 1 subd3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\control2.rpt
control2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 outa0
186 - - - 27 OUTPUT 0 1 0 0 outa1
30 - - H -- OUTPUT 0 1 0 0 outa2
19 - - D -- OUTPUT 0 1 0 0 outa3
40 - - J -- OUTPUT 0 1 0 0 outb0
41 - - K -- OUTPUT 0 1 0 0 outb1
47 - - L -- OUTPUT 0 1 0 0 outb2
9 - - A -- OUTPUT 0 1 0 0 outb3
17 - - D -- OUTPUT 0 1 0 0 outc0
11 - - B -- OUTPUT 0 1 0 0 outc1
15 - - C -- OUTPUT 0 1 0 0 outc2
14 - - C -- OUTPUT 0 1 0 0 outc3
71 - - - 30 OUTPUT 0 1 0 0 outd0
26 - - F -- OUTPUT 0 1 0 0 outd1
31 - - H -- OUTPUT 0 1 0 0 outd2
16 - - D -- OUTPUT 0 1 0 0 outd3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\control2.rpt
control2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - H 43 OR2 4 0 0 17 :115
- 6 - A 28 AND2 1 1 0 1 :117
- 4 - K 48 AND2 1 1 0 1 :119
- 7 - H 43 AND2 1 1 0 1 :121
- 7 - D 30 AND2 1 1 0 1 :123
- 1 - K 31 AND2 1 1 0 1 :125
- 3 - K 31 AND2 1 1 0 1 :127
- 1 - K 48 AND2 1 1 0 1 :129
- 1 - A 28 AND2 1 1 0 1 :131
- 3 - K 48 AND2 1 1 0 1 :133
- 3 - C 36 AND2 1 1 0 1 :135
- 2 - K 48 AND2 1 1 0 1 :137
- 7 - C 36 AND2 1 1 0 1 :139
- 4 - F 29 AND2 1 1 0 1 :141
- 7 - F 29 AND2 1 1 0 1 :143
- 4 - H 43 AND2 1 1 0 1 :145
- 1 - D 30 AND2 1 1 0 1 :147
- 1 - H 43 AND2 ! 4 0 0 17 :153
- 2 - H 43 AND2 ! 4 0 0 17 :193
- 2 - F 29 AND2 0 3 0 16 :228
- 7 - A 28 OR2 s 2 2 0 1 ~230~1
- 2 - A 28 OR2 1 3 1 0 :230
- 8 - A 28 OR2 s 2 2 0 1 ~232~1
- 5 - A 28 OR2 1 3 1 0 :232
- 8 - H 43 OR2 s 2 2 0 1 ~234~1
- 3 - H 43 OR2 1 3 1 0 :234
- 8 - D 30 OR2 s 2 2 0 1 ~236~1
- 6 - D 30 OR2 1 3 1 0 :236
- 2 - K 31 OR2 s 2 2 0 1 ~238~1
- 7 - K 31 OR2 1 3 1 0 :238
- 4 - K 31 OR2 s 2 2 0 1 ~240~1
- 5 - K 31 OR2 1 3 1 0 :240
- 6 - K 31 OR2 s 2 2 0 1 ~242~1
- 8 - K 31 OR2 1 3 1 0 :242
- 4 - A 28 OR2 s 2 2 0 1 ~244~1
- 3 - A 28 OR2 1 3 1 0 :244
- 5 - D 30 OR2 s 2 2 0 1 ~246~1
- 3 - D 30 OR2 1 3 1 0 :246
- 4 - C 36 OR2 s 2 2 0 1 ~248~1
- 1 - C 36 OR2 1 3 1 0 :248
- 5 - C 36 OR2 s 2 2 0 1 ~250~1
- 6 - C 36 OR2 1 3 1 0 :250
- 8 - C 36 OR2 s 2 2 0 1 ~252~1
- 2 - C 36 OR2 1 3 1 0 :252
- 5 - F 29 OR2 s 2 2 0 1 ~254~1
- 6 - F 29 OR2 1 3 1 0 :254
- 8 - F 29 OR2 s 2 2 0 1 ~256~1
- 3 - F 29 OR2 1 3 1 0 :256
- 1 - F 29 OR2 s 2 2 0 1 ~258~1
- 5 - H 43 OR2 1 3 1 0 :258
- 4 - D 30 OR2 s 2 2 0 1 ~260~1
- 2 - D 30 OR2 1 3 1 0 :260
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\control2.rpt
control2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/208( 4%) 0/104( 0%) 8/104( 7%) 5/16( 31%) 2/16( 12%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 7/208( 3%) 0/104( 0%) 11/104( 10%) 4/16( 25%) 2/16( 12%) 0/16( 0%)
D: 8/208( 3%) 0/104( 0%) 11/104( 10%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 5/208( 2%) 0/104( 0%) 7/104( 6%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 5/208( 2%) 0/104( 0%) 5/104( 4%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
K: 7/208( 3%) 0/104( 0%) 14/104( 13%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
28: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
29: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
31: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
36: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
37: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
38: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
39: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
40: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
41: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
42: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
43: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
44: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
45: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
46: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
47: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
48: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
49: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
50: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
51: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
52: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\control2.rpt
control2
** EQUATIONS **
adda0 : INPUT;
adda1 : INPUT;
adda2 : INPUT;
adda3 : INPUT;
addb0 : INPUT;
addb1 : INPUT;
addb2 : INPUT;
addb3 : INPUT;
addc0 : INPUT;
addc1 : INPUT;
addc2 : INPUT;
addc3 : INPUT;
addd0 : INPUT;
addd1 : INPUT;
addd2 : INPUT;
addd3 : INPUT;
conl0 : INPUT;
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