bcdto2.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,260 行 · 第 1/5 页

-- Equation name is '_LC5_I28', type is buried 
_LC5_I28 = LCELL( _EQ055);
  _EQ055 = !C0 &  C1 & !C2 & !C3
         # !C1 &  C2 & !C3
         #  C0 &  C2 & !C3
         #  C0 & !C1 & !C2 &  C3;

-- Node name is '|BCDTOB3:3|:976' 
-- Equation name is '_LC4_I28', type is buried 
_LC4_I28 = LCELL( _EQ056);
  _EQ056 =  C0 & !C1 & !C3
         # !C0 &  C1 & !C3;

-- Node name is '|BCDTOB3:3|:1009' 
-- Equation name is '_LC7_I28', type is buried 
_LC7_I28 = LCELL( _EQ057);
  _EQ057 =  C0 & !C3
         # !C0 & !C1 & !C2 &  C3;

-- Node name is '|BCDTOB3:3|:1042' 
-- Equation name is '_LC8_I28', type is buried 
_LC8_I28 = LCELL( _EQ058);
  _EQ058 =  C2 & !C3;

-- Node name is '|BCDTOB3:3|:1075' 
-- Equation name is '_LC8_I45', type is buried 
_LC8_I45 = LCELL( _EQ059);
  _EQ059 =  C1 & !C3;

-- Node name is '|BCDTOB3:3|:1108' 
-- Equation name is '_LC3_I28', type is buried 
_LC3_I28 = LCELL( _EQ060);
  _EQ060 =  C0 & !C3
         #  C0 & !C1 & !C2;

-- Node name is '|BCDTOB4:4|:566' 
-- Equation name is '_LC3_I48', type is buried 
_LC3_I48 = LCELL( _EQ061);
  _EQ061 =  D0 & !D1 & !D2 &  D3;

-- Node name is '|BCDTOB4:4|:650' 
-- Equation name is '_LC6_I48', type is buried 
_LC6_I48 = LCELL( _EQ062);
  _EQ062 = !D0 &  D1 & !D2 & !D3;

-- Node name is '|BCDTOB4:4|:662' 
-- Equation name is '_LC4_I48', type is buried 
_LC4_I48 = LCELL( _EQ063);
  _EQ063 =  D0 & !D1 & !D2 & !D3;

-- Node name is '|BCDTOB4:4|:674' 
-- Equation name is '_LC1_I48', type is buried 
!_LC1_I48 = _LC1_I48~NOT;
_LC1_I48~NOT = LCELL( _EQ064);
  _EQ064 =  D2
         #  D1
         #  D0
         #  D3;

-- Node name is '|BCDTOB4:4|:761' 
-- Equation name is '_LC2_I49', type is buried 
_LC2_I49 = LCELL( _EQ065);
  _EQ065 = !D0 & !D1 & !D2 &  D3
         #  D1 &  D2 & !D3
         #  D0 &  D2 & !D3;

-- Node name is '|BCDTOB4:4|~778~1' 
-- Equation name is '_LC3_I51', type is buried 
-- synthesized logic cell 
!_LC3_I51 = _LC3_I51~NOT;
_LC3_I51~NOT = LCELL( _EQ066);
  _EQ066 =  _LC4_I48
         #  _LC6_I48
         # !_LC7_I48;

-- Node name is '|BCDTOB4:4|:778' 
-- Equation name is '_LC8_I51', type is buried 
_LC8_I51 = LCELL( _EQ067);
  _EQ067 = !_LC1_I48 &  _LC2_I49 &  _LC3_I51;

-- Node name is '|BCDTOB4:4|:799' 
-- Equation name is '_LC5_I48', type is buried 
_LC5_I48 = LCELL( _EQ068);
  _EQ068 = !D0 & !D1 & !D2 &  D3
         #  D0 &  D1 &  D2 & !D3;

-- Node name is '|BCDTOB4:4|~811~1' 
-- Equation name is '_LC4_I51', type is buried 
-- synthesized logic cell 
_LC4_I51 = LCELL( _EQ069);
  _EQ069 = !_LC1_I48 & !_LC4_I48;

-- Node name is '|BCDTOB4:4|:811' 
-- Equation name is '_LC7_I51', type is buried 
_LC7_I51 = LCELL( _EQ070);
  _EQ070 =  _LC4_I51 &  _LC5_I48 & !_LC6_I48
         #  _LC4_I51 & !_LC6_I48 & !_LC7_I48;

-- Node name is '|BCDTOB4:4|:844' 
-- Equation name is '_LC6_I52', type is buried 
_LC6_I52 = LCELL( _EQ071);
  _EQ071 = !D0 &  D2 & !D3
         # !D0 & !D1 & !D2 &  D3
         # !D0 &  D1 & !D3;

-- Node name is '|BCDTOB4:4|:877' 
-- Equation name is '_LC1_I51', type is buried 
_LC1_I51 = LCELL( _EQ072);
  _EQ072 = !_LC1_I48 &  _LC2_I49
         # !_LC1_I48 & !_LC3_I51
         # !_LC1_I48 &  _LC3_I48;

-- Node name is '|BCDTOB4:4|:943' 
-- Equation name is '_LC8_I47', type is buried 
_LC8_I47 = LCELL( _EQ073);
  _EQ073 =  D0 & !D1 & !D3
         #  D1 & !D2 & !D3
         #  D0 & !D2 & !D3
         # !D1 &  D2 & !D3;

-- Node name is '|BCDTOB4:4|~970~1' 
-- Equation name is '_LC7_I48', type is buried 
-- synthesized logic cell 
!_LC7_I48 = _LC7_I48~NOT;
_LC7_I48~NOT = LCELL( _EQ074);
  _EQ074 =  D0 &  D1 & !D2 & !D3
         # !D0 & !D1 &  D2 & !D3;

-- Node name is '|BCDTOB4:4|:970' 
-- Equation name is '_LC1_I46', type is buried 
_LC1_I46 = LCELL( _EQ075);
  _EQ075 = !D0 & !D1 & !D2 &  D3
         #  D1 &  D2 & !D3;

-- Node name is '|BCDTOB4:4|:976' 
-- Equation name is '_LC1_I47', type is buried 
_LC1_I47 = LCELL( _EQ076);
  _EQ076 = !_LC1_I48 &  _LC4_I48
         # !_LC1_I48 &  _LC6_I48
         #  _LC1_I46 & !_LC1_I48;

-- Node name is '|BCDTOB4:4|:1009' 
-- Equation name is '_LC8_I48', type is buried 
_LC8_I48 = LCELL( _EQ077);
  _EQ077 =  D0 & !D2 & !D3
         # !D0 &  D2 & !D3
         #  D0 & !D1 & !D2;

-- Node name is '|BCDTOB4:4|:1042' 
-- Equation name is '_LC1_I49', type is buried 
_LC1_I49 = LCELL( _EQ078);
  _EQ078 =  D1 & !D3;

-- Node name is '|BCDTOB4:4|:1075' 
-- Equation name is '_LC2_I48', type is buried 
_LC2_I48 = LCELL( _EQ079);
  _EQ079 =  D0 & !D3
         #  D0 & !D1 & !D2;



Project Information                              e:\electron\bcdto2\bcdto2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 55,855K