bcdto2.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,260 行 · 第 1/5 页

RPT
1,260
字号

Device-Specific Information:                     e:\electron\bcdto2\bcdto2.rpt
bcdto2

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  60      -     -    -    40      INPUT             ^    0    0    0    1  A0
  63      -     -    -    35      INPUT             ^    0    0    0    3  A1
  53      -     -    -    52      INPUT             ^    0    0    0    4  A2
  70      -     -    -    31      INPUT             ^    0    0    0    5  A3
 198      -     -    -    44      INPUT             ^    0    0    0    6  B0
 187      -     -    -    28      INPUT             ^    0    0    0    7  B1
 195      -     -    -    39      INPUT             ^    0    0    0    7  B2
 186      -     -    -    27      INPUT             ^    0    0    0    8  B3
 116      -     -    I    --      INPUT             ^    0    0    0    6  C0
 183      -     -    -    --      INPUT             ^    0    0    0    8  C1
  73      -     -    -    29      INPUT             ^    0    0    0    7  C2
  79      -     -    -    --      INPUT             ^    0    0    0    9  C3
  78      -     -    -    --      INPUT             ^    0    0    0   12  D0
 182      -     -    -    --      INPUT             ^    0    0    0   13  D1
 184      -     -    -    --      INPUT             ^    0    0    0   12  D2
  80      -     -    -    --      INPUT             ^    0    0    0   13  D3


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                     e:\electron\bcdto2\bcdto2.rpt
bcdto2

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
 192      -     -    -    37     OUTPUT                 0    1    0    0  O0
  26      -     -    F    --     OUTPUT                 0    1    0    0  O1
 199      -     -    -    45     OUTPUT                 0    1    0    0  O2
 200      -     -    -    46     OUTPUT                 0    1    0    0  O3
  74      -     -    -    28     OUTPUT                 0    1    0    0  O4
  75      -     -    -    27     OUTPUT                 0    1    0    0  O5
 203      -     -    -    48     OUTPUT                 0    1    0    0  O6
 202      -     -    -    47     OUTPUT                 0    1    0    0  O7
 208      -     -    -    52     OUTPUT                 0    1    0    0  O8
  47      -     -    L    --     OUTPUT                 0    1    0    0  O9
 207      -     -    -    51     OUTPUT                 0    1    0    0  O10
  37      -     -    I    --     OUTPUT                 0    1    0    0  O11
  38      -     -    I    --     OUTPUT                 0    1    0    0  O12
  54      -     -    -    51     OUTPUT                 0    1    0    0  O13
 163      -     -    -    14     OUTPUT                 0    0    0    0  O14
  64      -     -    -    35     OUTPUT                 0    0    0    0  O15


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                     e:\electron\bcdto2\bcdto2.rpt
bcdto2

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      3     -    I    45        OR2                0    2    1    0  |add16:5|:99
   -      6     -    I    45        OR2                0    4    0    3  |add16:5|:106
   -      5     -    I    45        OR2                0    4    0    2  |add16:5|:110
   -      2     -    I    38        OR2                0    4    0    2  |add16:5|:112
   -      8     -    I    38        OR2                0    4    0    1  |add16:5|:115
   -      4     -    I    50        OR2    s           4    0    0    1  |add16:5|~116~1
   -      1     -    I    38        OR2                0    4    0    4  |add16:5|:116
   -      3     -    I    27        OR2                0    3    0    2  |add16:5|:124
   -      4     -    I    38       AND2                0    3    0    1  |add16:5|:127
   -      3     -    I    50        OR2                0    3    0    2  |add16:5|:130
   -      2     -    I    45        OR2                0    2    1    0  |add16:6|:105
   -      4     -    I    45        OR2                0    4    0    3  |add16:6|:112
   -      1     -    I    45        OR2                0    4    0    2  |add16:6|:116
   -      4     -    I    27        OR2                0    4    0    2  |add16:6|:118
   -      7     -    I    27        OR2                0    4    0    3  |add16:6|:122
   -      2     -    I    28        OR2                0    2    0    3  |add16:6|:126
   -      6     -    I    28        OR2    s           4    0    0    1  |add16:6|~128~1
   -      1     -    I    27        OR2                0    4    0    3  |add16:6|:128
   -      4     -    I    47        OR2                0    2    0    3  |add16:6|:132
   -      2     -    I    47        OR2                0    4    0    4  |add16:6|:134
   -      2     -    I    40        OR2                0    3    0    3  |add16:6|:142
   -      1     -    I    40       AND2                0    3    0    3  |add16:6|:145
   -      4     -    I    52        OR2                0    2    0    2  |add16:6|:148
   -      7     -    I    45        OR2                0    2    1    0  |add16:7|:111
   -      6     -    I    27        OR2                0    4    1    0  |add16:7|:118
   -      5     -    I    27        OR2                0    4    0    2  |add16:7|:122
   -      8     -    I    27        OR2                0    4    1    0  |add16:7|:124
   -      2     -    I    27        OR2                0    4    0    2  |add16:7|:128
   -      6     -    I    47        OR2                0    4    1    0  |add16:7|:130
   -      7     -    I    47        OR2                0    4    0    2  |add16:7|:134
   -      5     -    I    47        OR2                0    4    1    0  |add16:7|:136
   -      3     -    I    47        OR2                0    4    0    3  |add16:7|:140
   -      7     -    I    52        OR2                0    3    1    0  |add16:7|:142
   -      8     -    I    52        OR2                0    4    1    0  |add16:7|:148
   -      5     -    I    52        OR2                0    4    0    2  |add16:7|:152
   -      2     -    I    52        OR2                0    4    1    0  |add16:7|:154
   -      1     -    I    52        OR2                0    4    0    3  |add16:7|:158
   -      2     -    I    51        OR2                0    2    1    0  |add16:7|:160
   -      5     -    I    51        OR2                0    3    1    0  |add16:7|:166
   -      6     -    I    51        OR2                0    4    1    0  |add16:7|:172
   -      6     -    I    38       AND2    s           3    0    0    3  |BCDTOB1:1|~1075~1
   -      7     -    I    38        OR2    s           2    0    0    3  |BCDTOB1:1|~1075~2
   -      1     -    I    35       AND2                2    0    0    2  |BCDTOB1:1|:1108
   -      3     -    I    38       AND2                2    0    0    3  |BCDTOB1:1|:1141
   -      5     -    I    38        OR2                4    0    1    0  |BCDTOB1:1|:1174
   -      6     -    I    50        OR2    s           2    0    0    1  |BCDTOB2:2|~976~1
   -      8     -    I    50        OR2    s           4    0    0    1  |BCDTOB2:2|~976~2
   -      2     -    I    50        OR2                4    0    0    2  |BCDTOB2:2|:1009
   -      1     -    I    50        OR2                4    0    0    4  |BCDTOB2:2|:1042
   -      7     -    I    50        OR2                4    0    0    2  |BCDTOB2:2|:1075
   -      1     -    I    34       AND2                2    0    0    2  |BCDTOB2:2|:1108
   -      5     -    I    50        OR2                4    0    0    3  |BCDTOB2:2|:1141
   -      3     -    I    52        OR2                3    0    0    3  |BCDTOB3:3|:877
   -      1     -    I    28        OR2                4    0    0    2  |BCDTOB3:3|:910
   -      5     -    I    28        OR2                4    0    0    4  |BCDTOB3:3|:943
   -      4     -    I    28        OR2                3    0    0    2  |BCDTOB3:3|:976
   -      7     -    I    28        OR2                4    0    0    1  |BCDTOB3:3|:1009
   -      8     -    I    28       AND2                2    0    0    2  |BCDTOB3:3|:1042
   -      8     -    I    45       AND2                2    0    0    2  |BCDTOB3:3|:1075
   -      3     -    I    28        OR2                4    0    0    3  |BCDTOB3:3|:1108
   -      3     -    I    48       AND2                4    0    0    2  |BCDTOB4:4|:566
   -      6     -    I    48       AND2                4    0    0    3  |BCDTOB4:4|:650
   -      4     -    I    48       AND2                4    0    0    3  |BCDTOB4:4|:662
   -      1     -    I    48        OR2        !       4    0    0    4  |BCDTOB4:4|:674
   -      2     -    I    49        OR2                4    0    0    2  |BCDTOB4:4|:761
   -      3     -    I    51        OR2    s   !       0    3    0    2  |BCDTOB4:4|~778~1
   -      8     -    I    51       AND2                0    3    0    2  |BCDTOB4:4|:778
   -      5     -    I    48        OR2                4    0    0    1  |BCDTOB4:4|:799
   -      4     -    I    51       AND2    s           0    2    0    1  |BCDTOB4:4|~811~1
   -      7     -    I    51        OR2                0    4    0    3  |BCDTOB4:4|:811
   -      6     -    I    52        OR2                4    0    0    2  |BCDTOB4:4|:844
   -      1     -    I    51        OR2                0    4    0    3  |BCDTOB4:4|:877
   -      8     -    I    47        OR2                4    0    0    2  |BCDTOB4:4|:943
   -      7     -    I    48        OR2    s   !       4    0    0    2  |BCDTOB4:4|~970~1
   -      1     -    I    46        OR2                4    0    0    1  |BCDTOB4:4|:970
   -      1     -    I    47        OR2                0    4    0    2  |BCDTOB4:4|:976
   -      8     -    I    48        OR2                4    0    0    2  |BCDTOB4:4|:1009
   -      1     -    I    49       AND2                2    0    0    2  |BCDTOB4:4|:1042
   -      2     -    I    48        OR2                4    0    0    3  |BCDTOB4:4|:1075


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                     e:\electron\bcdto2\bcdto2.rpt
bcdto2

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
E:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
F:       0/208(  0%)     0/104(  0%)     1/104(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
G:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
H:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
I:       9/208(  4%)     0/104(  0%)    45/104( 43%)    1/16(  6%)      2/16( 12%)     0/16(  0%)
J:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
K:       0/208(  0%)     0/104(  0%)     0/104(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
L:       0/208(  0%)     0/104(  0%)     1/104(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
28:      2/24(  8%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
29:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
30:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      1/24(  4%)     1/4( 25%)      1/4( 25%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
37:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
38:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
39:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
40:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
41:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
42:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
45:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
46:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
47:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)

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