display.rpt

ProtelDXp 实现计算器功能

-- Node name is ':353' 
-- Equation name is '_LC4_A5', type is buried 
!_LC4_A5 = _LC4_A5~NOT;
_LC4_A5~NOT = LCELL( _EQ007);
  _EQ007 = !_LC6_A5 & !_LC6_A22
         # !AIN3 & !_LC6_A5
         # !AIN3 &  _LC6_A22;

-- Node name is ':359' 
-- Equation name is '_LC2_A21', type is buried 
_LC2_A21 = LCELL( _EQ008);
  _EQ008 =  CIN2 &  _LC3_A22
         #  DIN2 & !_LC3_A22;

-- Node name is ':362' 
-- Equation name is '_LC3_A21', type is buried 
_LC3_A21 = LCELL( _EQ009);
  _EQ009 =  _LC2_A21 & !_LC2_A22
         #  BIN2 &  _LC2_A22;

-- Node name is ':365' 
-- Equation name is '_LC1_A21', type is buried 
_LC1_A21 = LCELL( _EQ010);
  _EQ010 =  _LC3_A21 & !_LC6_A22
         #  AIN2 &  _LC6_A22;

-- Node name is ':371' 
-- Equation name is '_LC7_A5', type is buried 
_LC7_A5  = LCELL( _EQ011);
  _EQ011 =  CIN1 &  _LC3_A22
         #  DIN1 & !_LC3_A22;

-- Node name is ':374' 
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = LCELL( _EQ012);
  _EQ012 = !_LC2_A22 &  _LC7_A5
         #  BIN1 &  _LC2_A22;

-- Node name is ':377' 
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = LCELL( _EQ013);
  _EQ013 = !_LC6_A22 &  _LC8_A5
         #  AIN1 &  _LC6_A22;

-- Node name is ':383' 
-- Equation name is '_LC7_A22', type is buried 
!_LC7_A22 = _LC7_A22~NOT;
_LC7_A22~NOT = LCELL( _EQ014);
  _EQ014 = !CIN0 & !DIN0
         # !DIN0 & !_LC3_A22
         # !CIN0 &  _LC3_A22;

-- Node name is ':386' 
-- Equation name is '_LC8_A22', type is buried 
!_LC8_A22 = _LC8_A22~NOT;
_LC8_A22~NOT = LCELL( _EQ015);
  _EQ015 = !BIN0 & !_LC7_A22
         # !BIN0 &  _LC2_A22
         # !_LC2_A22 & !_LC7_A22;

-- Node name is ':389' 
-- Equation name is '_LC3_A5', type is buried 
!_LC3_A5 = _LC3_A5~NOT;
_LC3_A5~NOT = LCELL( _EQ016);
  _EQ016 = !AIN0 & !_LC8_A22
         # !AIN0 &  _LC6_A22
         # !_LC6_A22 & !_LC8_A22;

-- Node name is ':403' 
-- Equation name is '_LC5_A22', type is buried 
_LC5_A22 = LCELL( _EQ017);
  _EQ017 =  CNT0 & !_LC2_A22 & !_LC6_A22
         # !CNT1 & !_LC2_A22 & !_LC6_A22;

-- Node name is ':689' 
-- Equation name is '_LC3_A17', type is buried 
_LC3_A17 = LCELL( _EQ018);
  _EQ018 =  _LC1_A21 & !_LC2_A5 & !_LC3_A5 & !_LC4_A5;

-- Node name is ':713' 
-- Equation name is '_LC7_A2', type is buried 
!_LC7_A2 = _LC7_A2~NOT;
_LC7_A2~NOT = LCELL( _EQ019);
  _EQ019 = !_LC2_A5
         #  _LC4_A5
         #  _LC3_A5
         #  _LC1_A21;

-- Node name is ':725' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ020);
  _EQ020 = !_LC1_A21 & !_LC2_A5 &  _LC3_A5 & !_LC4_A5;

-- Node name is ':737' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ021);
  _EQ021 = !_LC1_A21 & !_LC2_A5 & !_LC3_A5 & !_LC4_A5;

-- Node name is '~775~1' 
-- Equation name is '~775~1', location is LC5_A2, type is buried.
-- synthesized logic cell 
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ022);
  _EQ022 =  _LC4_A2
         #  _LC2_A2;

-- Node name is ':775' 
-- Equation name is '_LC1_A5', type is buried 
_LC1_A5  = LCELL( _EQ023);
  _EQ023 =  _LC1_A21 & !_LC3_A5 & !_LC4_A5
         #  _LC1_A21 & !_LC2_A5 & !_LC4_A5
         #  _LC2_A5 & !_LC3_A5 & !_LC4_A5
         # !_LC1_A21 &  _LC2_A5 & !_LC4_A5
         # !_LC1_A21 & !_LC2_A5 &  _LC4_A5;

-- Node name is ':806' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = LCELL( _EQ024);
  _EQ024 =  _LC4_A17 &  _LC8_A17
         #  _LC3_A17 &  _LC4_A17
         #  _LC2_A2;

-- Node name is '~808~1' 
-- Equation name is '~808~1', location is LC4_A17, type is buried.
-- synthesized logic cell 
!_LC4_A17 = _LC4_A17~NOT;
_LC4_A17~NOT = LCELL( _EQ025);
  _EQ025 = !_LC1_A21 &  _LC2_A5 & !_LC4_A5
         # !_LC1_A21 &  _LC3_A5 & !_LC4_A5;

-- Node name is '~835~1' 
-- Equation name is '~835~1', location is LC6_A2, type is buried.
-- synthesized logic cell 
!_LC6_A2 = _LC6_A2~NOT;
_LC6_A2~NOT = LCELL( _EQ026);
  _EQ026 =  _LC1_A21 & !_LC2_A5 & !_LC3_A5 & !_LC4_A5
         # !_LC1_A21 &  _LC2_A5 &  _LC3_A5 & !_LC4_A5;

-- Node name is ':839' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = LCELL( _EQ027);
  _EQ027 = !_LC1_A21 & !_LC3_A5 & !_LC4_A5
         # !_LC1_A21 & !_LC2_A5 & !_LC3_A5
         #  _LC2_A5 & !_LC3_A5 & !_LC4_A5;

-- Node name is ':857' 
-- Equation name is '_LC8_A17', type is buried 
_LC8_A17 = LCELL( _EQ028);
  _EQ028 = !_LC1_A21 & !_LC2_A5 &  _LC4_A5
         #  _LC1_A21 & !_LC2_A5 &  _LC3_A5 & !_LC4_A5
         #  _LC1_A21 &  _LC2_A5 & !_LC3_A5 & !_LC4_A5;

-- Node name is ':872' 
-- Equation name is '_LC2_A17', type is buried 
_LC2_A17 = LCELL( _EQ029);
  _EQ029 = !_LC1_A21 & !_LC3_A5 & !_LC4_A5
         # !_LC1_A21 &  _LC2_A5 & !_LC4_A5
         # !_LC1_A21 & !_LC2_A5 &  _LC4_A5
         # !_LC1_A21 & !_LC2_A5 & !_LC3_A5
         #  _LC2_A5 & !_LC3_A5 & !_LC4_A5
         #  _LC1_A21 & !_LC2_A5 &  _LC3_A5 & !_LC4_A5;

-- Node name is ':905' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = LCELL( _EQ030);
  _EQ030 = !_LC5_A2
         # !_LC6_A2 & !_LC7_A2
         # !_LC7_A2 &  _LC8_A2;

-- Node name is ':928' 
-- Equation name is '_LC6_A17', type is buried 
_LC6_A17 = LCELL( _EQ031);
  _EQ031 = !_LC1_A21 & !_LC2_A5 &  _LC4_A5
         #  _LC1_A21 &  _LC2_A5 &  _LC3_A5 & !_LC4_A5;

-- Node name is ':938' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ032);
  _EQ032 =  _LC2_A2
         #  _LC3_A17
         # !_LC4_A17
         #  _LC6_A17;

-- Node name is ':956' 
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ033);
  _EQ033 =  _LC1_A21 &  _LC3_A5 & !_LC4_A5
         # !_LC1_A21 & !_LC2_A5 &  _LC4_A5
         #  _LC1_A21 &  _LC2_A5 & !_LC4_A5;

-- Node name is ':971' 
-- Equation name is '_LC7_A17', type is buried 
_LC7_A17 = LCELL( _EQ034);
  _EQ034 = !_LC1_A21 & !_LC3_A5 & !_LC4_A5
         #  _LC1_A21 &  _LC3_A5 & !_LC4_A5
         # !_LC1_A21 & !_LC2_A5 &  _LC4_A5
         # !_LC1_A21 & !_LC2_A5 & !_LC3_A5
         #  _LC2_A5 & !_LC4_A5;



Project Information                                         e:\cal\display.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:05
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 54,295K