display.rpt
字号:
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
148 - - A -- OUTPUT 0 1 0 0 COM0
8 - - A -- OUTPUT 0 1 0 0 COM1
149 - - A -- OUTPUT 0 1 0 0 COM2
173 - - - 21 OUTPUT 0 1 0 0 COM3
89 - - - 18 OUTPUT 0 1 0 0 SEG0
7 - - A -- OUTPUT 0 1 0 0 SEG1
103 - - - 02 OUTPUT 0 1 0 0 SEG2
150 - - A -- OUTPUT 0 1 0 0 SEG3
169 - - - 18 OUTPUT 0 1 0 0 SEG4
168 - - - 17 OUTPUT 0 1 0 0 SEG5
100 - - - 05 OUTPUT 0 1 0 0 SEG6
12 - - B -- OUTPUT 0 0 0 0 SEG7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\display.rpt
display
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 22 DFFE + 0 1 0 4 CNT1 (:30)
- 1 - A 22 DFFE + 0 0 0 5 CNT0 (:31)
- 3 - A 22 OR2 ! 0 2 1 4 :334
- 5 - A 05 OR2 ! 2 1 0 1 :337
- 2 - A 22 OR2 ! 0 2 1 5 :342
- 6 - A 05 OR2 ! 1 2 0 1 :345
- 6 - A 22 OR2 ! 0 2 1 5 :350
- 4 - A 05 OR2 ! 1 2 0 13 :353
- 2 - A 21 OR2 2 1 0 1 :359
- 3 - A 21 OR2 1 2 0 1 :362
- 1 - A 21 OR2 1 2 0 13 :365
- 7 - A 05 OR2 2 1 0 1 :371
- 8 - A 05 OR2 1 2 0 1 :374
- 2 - A 05 OR2 1 2 0 13 :377
- 7 - A 22 OR2 ! 2 1 0 1 :383
- 8 - A 22 OR2 ! 1 2 0 1 :386
- 3 - A 05 OR2 ! 1 2 0 13 :389
- 5 - A 22 OR2 0 4 1 0 :403
- 3 - A 17 AND2 0 4 0 2 :689
- 7 - A 02 OR2 ! 0 4 0 1 :713
- 4 - A 02 AND2 0 4 0 1 :725
- 2 - A 02 AND2 0 4 0 3 :737
- 5 - A 02 OR2 s ! 0 2 0 1 ~775~1
- 1 - A 05 OR2 0 4 1 0 :775
- 1 - A 17 OR2 0 4 1 0 :806
- 4 - A 17 OR2 s ! 0 4 0 2 ~808~1
- 6 - A 02 OR2 s ! 0 4 0 1 ~835~1
- 5 - A 17 OR2 0 4 1 0 :839
- 8 - A 17 OR2 0 4 0 1 :857
- 2 - A 17 OR2 0 4 1 0 :872
- 3 - A 02 OR2 0 4 1 0 :905
- 6 - A 17 OR2 0 4 0 1 :928
- 1 - A 02 OR2 0 4 1 0 :938
- 8 - A 02 OR2 0 4 0 1 :956
- 7 - A 17 OR2 0 4 1 0 :971
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/208( 3%) 18/104( 17%) 0/104( 0%) 2/16( 12%) 5/16( 31%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 2 CLK
Device-Specific Information: e:\cal\display.rpt
display
** EQUATIONS **
AIN0 : INPUT;
AIN1 : INPUT;
AIN2 : INPUT;
AIN3 : INPUT;
BIN0 : INPUT;
BIN1 : INPUT;
BIN2 : INPUT;
BIN3 : INPUT;
CIN0 : INPUT;
CIN1 : INPUT;
CIN2 : INPUT;
CIN3 : INPUT;
CLK : INPUT;
DIN0 : INPUT;
DIN1 : INPUT;
DIN2 : INPUT;
DIN3 : INPUT;
-- Node name is ':31' = 'CNT0'
-- Equation name is 'CNT0', location is LC1_A22, type is buried.
CNT0 = DFFE(!CNT0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':30' = 'CNT1'
-- Equation name is 'CNT1', location is LC4_A22, type is buried.
CNT1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CNT0 & CNT1
# CNT0 & !CNT1;
-- Node name is 'COM0'
-- Equation name is 'COM0', type is output
COM0 = _LC6_A22;
-- Node name is 'COM1'
-- Equation name is 'COM1', type is output
COM1 = _LC2_A22;
-- Node name is 'COM2'
-- Equation name is 'COM2', type is output
COM2 = _LC3_A22;
-- Node name is 'COM3'
-- Equation name is 'COM3', type is output
COM3 = _LC5_A22;
-- Node name is 'SEG0'
-- Equation name is 'SEG0', type is output
SEG0 = _LC7_A17;
-- Node name is 'SEG1'
-- Equation name is 'SEG1', type is output
SEG1 = _LC1_A2;
-- Node name is 'SEG2'
-- Equation name is 'SEG2', type is output
SEG2 = _LC3_A2;
-- Node name is 'SEG3'
-- Equation name is 'SEG3', type is output
SEG3 = _LC2_A17;
-- Node name is 'SEG4'
-- Equation name is 'SEG4', type is output
SEG4 = _LC5_A17;
-- Node name is 'SEG5'
-- Equation name is 'SEG5', type is output
SEG5 = _LC1_A17;
-- Node name is 'SEG6'
-- Equation name is 'SEG6', type is output
SEG6 = _LC1_A5;
-- Node name is 'SEG7'
-- Equation name is 'SEG7', type is output
SEG7 = GND;
-- Node name is ':334'
-- Equation name is '_LC3_A22', type is buried
!_LC3_A22 = _LC3_A22~NOT;
_LC3_A22~NOT = LCELL( _EQ002);
_EQ002 = CNT0
# !CNT1;
-- Node name is ':337'
-- Equation name is '_LC5_A5', type is buried
!_LC5_A5 = _LC5_A5~NOT;
_LC5_A5~NOT = LCELL( _EQ003);
_EQ003 = !CIN3 & _LC3_A22
# !CIN3 & !DIN3
# !DIN3 & !_LC3_A22;
-- Node name is ':342'
-- Equation name is '_LC2_A22', type is buried
!_LC2_A22 = _LC2_A22~NOT;
_LC2_A22~NOT = LCELL( _EQ004);
_EQ004 = !CNT0
# CNT1;
-- Node name is ':345'
-- Equation name is '_LC6_A5', type is buried
!_LC6_A5 = _LC6_A5~NOT;
_LC6_A5~NOT = LCELL( _EQ005);
_EQ005 = !_LC2_A22 & !_LC5_A5
# !BIN3 & !_LC5_A5
# !BIN3 & _LC2_A22;
-- Node name is ':350'
-- Equation name is '_LC6_A22', type is buried
!_LC6_A22 = _LC6_A22~NOT;
_LC6_A22~NOT = LCELL( _EQ006);
_EQ006 = CNT0
# CNT1;
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