bcdtob1.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 586 行 · 第 1/3 页

50:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
51:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                    e:\electron\bcdto2\bcdtob1.rpt
bcdtob1

** EQUATIONS **

NUM0     : INPUT;
NUM1     : INPUT;
NUM2     : INPUT;
NUM3     : INPUT;

-- Node name is 'CO0' 
-- Equation name is 'CO0', type is output 
CO0      =  _LC1_A32;

-- Node name is 'CO1' 
-- Equation name is 'CO1', type is output 
CO1      =  _LC2_A32;

-- Node name is 'CO2' 
-- Equation name is 'CO2', type is output 
CO2      =  _LC3_A32;

-- Node name is 'CO3' 
-- Equation name is 'CO3', type is output 
CO3      =  _LC4_A32;

-- Node name is 'CO4' 
-- Equation name is 'CO4', type is output 
CO4      =  GND;

-- Node name is 'CO5' 
-- Equation name is 'CO5', type is output 
CO5      =  GND;

-- Node name is 'CO6' 
-- Equation name is 'CO6', type is output 
CO6      =  GND;

-- Node name is 'CO7' 
-- Equation name is 'CO7', type is output 
CO7      =  GND;

-- Node name is 'CO8' 
-- Equation name is 'CO8', type is output 
CO8      =  GND;

-- Node name is 'CO9' 
-- Equation name is 'CO9', type is output 
CO9      =  GND;

-- Node name is 'CO10' 
-- Equation name is 'CO10', type is output 
CO10     =  GND;

-- Node name is 'CO11' 
-- Equation name is 'CO11', type is output 
CO11     =  GND;

-- Node name is 'CO12' 
-- Equation name is 'CO12', type is output 
CO12     =  GND;

-- Node name is 'CO13' 
-- Equation name is 'CO13', type is output 
CO13     =  GND;

-- Node name is 'CO14' 
-- Equation name is 'CO14', type is output 
CO14     =  GND;

-- Node name is 'CO15' 
-- Equation name is 'CO15', type is output 
CO15     =  GND;

-- Node name is ':1075' 
-- Equation name is '_LC4_A32', type is buried 
_LC4_A32 = LCELL( _EQ001);
  _EQ001 = !NUM1 & !NUM2 &  NUM3;

-- Node name is ':1108' 
-- Equation name is '_LC3_A32', type is buried 
_LC3_A32 = LCELL( _EQ002);
  _EQ002 =  NUM2 & !NUM3;

-- Node name is ':1141' 
-- Equation name is '_LC2_A32', type is buried 
_LC2_A32 = LCELL( _EQ003);
  _EQ003 =  NUM1 & !NUM3;

-- Node name is ':1174' 
-- Equation name is '_LC1_A32', type is buried 
_LC1_A32 = LCELL( _EQ004);
  _EQ004 =  NUM0 & !NUM1 & !NUM2
         #  NUM0 & !NUM3;



Project Information                             e:\electron\bcdto2\bcdtob1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 50,825K