b16jianfa.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,211 行 · 第 1/5 页
RPT
1,211 行
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 8 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 5 0 0 0 0 0 36/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 0 8 0 0 0 0 0 0 0 1 0 1 0 8 0 8 8 0 0 0 8 0 58/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 7 0 8 0 0 0 0 0 0 8 1 0 1 0 8 0 8 13 0 0 0 8 0 94/0
Device-Specific Information: e:\cal\b16jianfa.rpt
b16jianfa
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - -- INPUT ^ 0 0 0 17 DEC
80 - - - -- INPUT ^ 0 0 0 17 EQUAL
93 - - - 14 INPUT ^ 0 0 0 5 N10
172 - - - 20 INPUT ^ 0 0 0 3 N11
100 - - - 05 INPUT ^ 0 0 0 3 N12
149 - - A -- INPUT ^ 0 0 0 2 N13
198 - - - 44 INPUT ^ 0 0 0 3 N14
69 - - - 32 INPUT ^ 0 0 0 2 N15
57 - - - 43 INPUT ^ 0 0 0 2 N16
75 - - - 27 INPUT ^ 0 0 0 3 N17
68 - - - 33 INPUT ^ 0 0 0 2 N18
143 - - B -- INPUT ^ 0 0 0 2 N19
183 - - - -- INPUT ^ 0 0 0 7 N20
159 - - - 11 INPUT ^ 0 0 0 5 N21
160 - - - 12 INPUT ^ 0 0 0 2 N22
79 - - - -- INPUT ^ 0 0 0 3 N23
190 - - - 33 INPUT ^ 0 0 0 5 N24
55 - - - 48 INPUT ^ 0 0 0 2 N25
64 - - - 35 INPUT ^ 0 0 0 3 N26
144 - - B -- INPUT ^ 0 0 0 5 N27
184 - - - -- INPUT ^ 0 0 0 2 N28
70 - - - 31 INPUT ^ 0 0 0 3 N29
62 - - - 36 INPUT ^ 0 0 0 3 N110
142 - - B -- INPUT ^ 0 0 0 2 N111
203 - - - 48 INPUT ^ 0 0 0 2 N112
191 - - - 35 INPUT ^ 0 0 0 3 N113
193 - - - 38 INPUT ^ 0 0 0 2 N114
205 - - - 50 INPUT ^ 0 0 0 2 N115
67 - - - 33 INPUT ^ 0 0 0 5 N210
182 - - - -- INPUT ^ 0 0 0 2 N211
199 - - - 45 INPUT ^ 0 0 0 3 N212
74 - - - 28 INPUT ^ 0 0 0 5 N213
60 - - - 40 INPUT ^ 0 0 0 2 N214
204 - - - 49 INPUT ^ 0 0 0 2 N215
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\b16jianfa.rpt
b16jianfa
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - A -- OUTPUT 0 1 0 0 CO0
148 - - A -- OUTPUT 0 1 0 0 CO1
7 - - A -- OUTPUT 0 1 0 0 CO2
10 - - A -- OUTPUT 0 1 0 0 CO3
195 - - - 39 OUTPUT 0 1 0 0 CO4
8 - - A -- OUTPUT 0 1 0 0 CO5
56 - - - 45 OUTPUT 0 1 0 0 CO6
13 - - B -- OUTPUT 0 1 0 0 CO7
12 - - B -- OUTPUT 0 1 0 0 CO8
54 - - - 51 OUTPUT 0 1 0 0 CO9
30 - - H -- OUTPUT 0 1 0 0 CO10
208 - - - 52 OUTPUT 0 1 0 0 CO11
147 - - B -- OUTPUT 0 1 0 0 CO12
187 - - - 28 OUTPUT 0 1 0 0 CO13
186 - - - 27 OUTPUT 0 1 0 0 CO14
11 - - B -- OUTPUT 0 1 0 0 CO15
150 - - A -- OUTPUT 0 1 0 0 S
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\b16jianfa.rpt
b16jianfa
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 08 OR2 ! 3 0 0 3 |LPM_ADD_SUB:275|addcore:adder|:115
- 7 - A 08 OR2 ! 1 1 0 5 |LPM_ADD_SUB:275|addcore:adder|:119
- 4 - A 30 OR2 ! 2 1 0 3 |LPM_ADD_SUB:275|addcore:adder|:127
- 2 - A 30 OR2 ! 1 1 0 5 |LPM_ADD_SUB:275|addcore:adder|:131
- 1 - B 40 OR2 ! 2 1 0 3 |LPM_ADD_SUB:275|addcore:adder|:139
- 3 - B 32 OR2 ! 1 1 0 5 |LPM_ADD_SUB:275|addcore:adder|:143
- 7 - B 44 OR2 ! 2 1 0 3 |LPM_ADD_SUB:275|addcore:adder|:151
- 4 - B 44 OR2 ! 1 1 0 5 |LPM_ADD_SUB:275|addcore:adder|:155
- 4 - B 47 OR2 ! 2 1 0 2 |LPM_ADD_SUB:275|addcore:adder|:163
- 6 - A 08 OR2 3 0 0 3 |LPM_ADD_SUB:275|addcore:adder|:180
- 7 - A 30 OR2 2 1 0 2 |LPM_ADD_SUB:275|addcore:adder|:183
- 7 - B 28 OR2 2 1 0 2 |LPM_ADD_SUB:275|addcore:adder|:186
- 2 - B 32 OR2 2 1 0 2 |LPM_ADD_SUB:275|addcore:adder|:189
- 7 - B 47 OR2 2 1 0 2 |LPM_ADD_SUB:275|addcore:adder|:192
- 5 - A 02 OR2 4 0 0 3 |LPM_ADD_SUB:276|addcore:adder|pcarry1
- 4 - A 02 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry2
- 4 - A 47 OR2 2 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry3
- 1 - A 47 OR2 0 3 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry4
- 6 - A 30 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry5
- 2 - B 28 OR2 2 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry6
- 4 - B 28 OR2 0 3 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry7
- 8 - B 28 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry8
- 5 - B 32 OR2 2 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry9
- 1 - B 32 OR2 0 3 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry10
- 8 - B 44 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry11
- 6 - B 44 OR2 2 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry12
- 6 - B 47 OR2 0 3 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry13
- 8 - B 47 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|pcarry14
- 5 - A 47 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:117
- 1 - A 30 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:118
- 3 - B 28 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:129
- 1 - B 28 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:130
- 7 - B 32 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:141
- 4 - B 32 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:142
- 3 - B 44 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:153
- 5 - B 47 OR2 2 1 0 1 |LPM_ADD_SUB:276|addcore:adder|:154
- 6 - A 02 OR2 4 0 0 1 |LPM_ADD_SUB:276|addcore:adder|:187
- 7 - A 02 OR2 1 2 0 1 |LPM_ADD_SUB:276|addcore:adder|:188
- 3 - A 47 OR2 2 2 0 4 |LPM_ADD_SUB:276|addcore:adder|:189
- 2 - A 47 OR2 2 2 0 3 |LPM_ADD_SUB:276|addcore:adder|:190
- 5 - A 30 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|:191
- 3 - A 30 OR2 2 2 0 4 |LPM_ADD_SUB:276|addcore:adder|:192
- 6 - B 28 OR2 2 2 0 3 |LPM_ADD_SUB:276|addcore:adder|:193
- 5 - B 28 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|:194
- 8 - B 32 OR2 2 2 0 4 |LPM_ADD_SUB:276|addcore:adder|:195
- 6 - B 32 OR2 2 2 0 3 |LPM_ADD_SUB:276|addcore:adder|:196
- 5 - B 44 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|:197
- 1 - B 44 OR2 2 2 0 3 |LPM_ADD_SUB:276|addcore:adder|:198
- 2 - B 44 OR2 2 2 0 2 |LPM_ADD_SUB:276|addcore:adder|:199
- 3 - B 47 OR2 1 2 0 2 |LPM_ADD_SUB:276|addcore:adder|:200
- 2 - B 47 OR2 2 2 0 1 |LPM_ADD_SUB:276|addcore:adder|:201
- 1 - B 47 OR2 2 2 0 16 |LPM_ADD_SUB:276|addcore:adder|:202
- 8 - A 02 OR2 4 0 0 2 |LPM_ADD_SUB:418|addcore:adder|:103
- 1 - A 02 OR2 1 3 0 4 |LPM_ADD_SUB:418|addcore:adder|:107
- 7 - A 39 AND2 0 2 0 1 |LPM_ADD_SUB:418|addcore:adder|:111
- 1 - A 39 AND2 0 4 0 4 |LPM_ADD_SUB:418|addcore:adder|:119
- 6 - B 46 AND2 0 2 0 1 |LPM_ADD_SUB:418|addcore:adder|:123
- 1 - B 46 AND2 0 4 0 4 |LPM_ADD_SUB:418|addcore:adder|:131
- 7 - B 51 AND2 0 2 0 1 |LPM_ADD_SUB:418|addcore:adder|:135
- 1 - B 51 AND2 0 4 0 3 |LPM_ADD_SUB:418|addcore:adder|:143
- 7 - B 27 AND2 0 3 0 2 |LPM_ADD_SUB:418|addcore:adder|:151
- 8 - A 08 AND2 2 0 0 1 :296
- 2 - B 27 OR2 0 4 0 1 :562
- 8 - B 27 OR2 0 3 0 1 :568
- 5 - B 27 OR2 0 4 0 1 :574
- 4 - B 27 OR2 0 3 0 1 :580
- 8 - B 51 OR2 0 4 0 1 :586
- 6 - B 51 OR2 0 4 0 1 :592
- 5 - B 51 OR2 0 3 0 1 :598
- 7 - B 46 OR2 0 4 0 1 :604
- 5 - B 46 OR2 0 4 0 1 :610
- 3 - B 46 OR2 0 3 0 1 :616
- 8 - A 39 OR2 0 4 0 1 :622
- 6 - A 39 OR2 0 4 0 1 :628
- 5 - A 39 OR2 0 3 0 1 :634
- 2 - A 02 OR2 0 3 0 1 :640
- 3 - A 02 OR2 2 2 0 1 :646
- 1 - B 42 OR2 2 1 1 0 :687
- 3 - B 27 OR2 2 1 1 0 :693
- 6 - B 27 OR2 2 1 1 0 :699
- 1 - B 27 OR2 2 1 1 0 :705
- 2 - B 51 OR2 2 1 1 0 :711
- 3 - B 51 OR2 2 1 1 0 :717
- 4 - B 51 OR2 2 1 1 0 :723
- 4 - B 46 OR2 2 1 1 0 :729
- 8 - B 46 OR2 2 1 1 0 :735
- 2 - B 46 OR2 2 1 1 0 :741
- 2 - A 39 OR2 2 1 1 0 :747
- 4 - A 39 OR2 2 1 1 0 :753
- 3 - A 39 OR2 2 1 1 0 :759
- 1 - A 08 OR2 2 1 1 0 :765
- 5 - A 08 OR2 2 1 1 0 :771
- 3 - A 08 OR2 2 1 1 0 :777
- 2 - A 08 OR2 2 1 1 0 :783
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\b16jianfa.rpt
b16jianfa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/208( 4%) 10/104( 9%) 12/104( 11%) 1/16( 6%) 6/16( 37%) 0/16( 0%)
B: 14/208( 6%) 0/104( 0%) 34/104( 32%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
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