mux16.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 612 行 · 第 1/5 页
RPT
612 行
K20 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 9/26( 34%)
K22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
K26 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 7/26( 26%)
K27 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
K29 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 9/26( 34%)
K30 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
K37 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
K41 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
K42 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
K47 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/26( 30%)
K48 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
K49 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
K50 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/26( 53%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 44/141 ( 31%)
Total logic cells used: 359/4992 ( 7%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 3.59/4 ( 89%)
Total fan-in: 1291/19968 ( 6%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 359
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 133/4992 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 2 8 0 8 8 8 0 8 8 0 7 8 0 8 0 8 0 0 8 8 1 8 8 8 0 8 0 0 8 0 8 8 0 8 8 0 8 0 0 8 8 0 0 0 8 0 8 8 0 0 8 0 1 227/0
D: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
G: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 8 0 0 0 8 0 0 0 8 0 0 0 1 0 0 1 7 0 0 8 0 1 0 0 0 8 0 8 0 8 8 0 0 0 0 0 0 1 0 0 0 8 8 0 0 0 0 8 8 8 8 0 0 123/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 10 8 0 8 16 8 0 8 17 0 7 8 1 8 0 9 7 0 8 16 1 9 8 8 0 16 0 16 8 8 16 8 0 8 8 0 8 1 0 8 8 8 8 0 8 0 8 16 8 8 16 0 1 359/0
Device-Specific Information: e:\cal\mux16.rpt
mux16
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
78 - - - -- INPUT ^ 0 0 0 30 a0
184 - - - -- INPUT ^ 0 0 0 32 a1
79 - - - -- INPUT ^ 0 0 0 35 a2
192 - - - 37 INPUT ^ 0 0 0 33 a3
75 - - - 27 INPUT ^ 0 0 0 31 a4
183 - - - -- INPUT ^ 0 0 0 25 a5
199 - - - 45 INPUT ^ 0 0 0 22 a6
57 - - - 43 INPUT ^ 0 0 0 20 a7
139 - - C -- INPUT ^ 0 0 0 17 a8
140 - - C -- INPUT ^ 0 0 0 15 a9
15 - - C -- INPUT ^ 0 0 0 13 a10
136 - - C -- INPUT ^ 0 0 0 12 a11
190 - - - 33 INPUT ^ 0 0 0 9 a12
86 - - - 23 INPUT ^ 0 0 0 7 a13
161 - - - 12 INPUT ^ 0 0 0 4 a14
113 - - K -- INPUT ^ 0 0 0 1 a15
182 - - - -- INPUT ^ 0 0 0 44 b0
64 - - - 35 INPUT ^ 0 0 0 42 b1
80 - - - -- INPUT ^ 0 0 0 27 b2
56 - - - 45 INPUT ^ 0 0 0 23 b3
208 - - - 52 INPUT ^ 0 0 0 28 b4
187 - - - 28 INPUT ^ 0 0 0 21 b5
94 - - - 13 INPUT ^ 0 0 0 27 b6
103 - - - 02 INPUT ^ 0 0 0 24 b7
69 - - - 32 INPUT ^ 0 0 0 15 b8
168 - - - 17 INPUT ^ 0 0 0 16 b9
14 - - C -- INPUT ^ 0 0 0 15 b10
96 - - - 08 INPUT ^ 0 0 0 10 b11
83 - - - 25 INPUT ^ 0 0 0 7 b12
164 - - - 14 INPUT ^ 0 0 0 4 b13
162 - - - 13 INPUT ^ 0 0 0 2 b14
114 - - K -- INPUT ^ 0 0 0 1 b15
18 - - D -- INPUT ^ 0 0 0 1 EQUAL
17 - - D -- INPUT ^ 0 0 0 1 MUL
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
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